Intel® SoC FPGAs use a bootloader to load and run the end user application on the hard processor system (HPS). The end user application may be a simple bare-metal application or a complex operating system like the Linux* operating system.
This page describes what a bootloader is, lists the available boot loaders and their main characteristics, describes how to get started with the bootloaders, and lists additional resources.
1. What is a Bootloader
When an SoC device boots up, a piece of software called the BootROM is first run. For several reasons, the BootROM has the following limited functionality:
- It needs to fit in the on-chip ROM so it has to be small
- It is very expensive to change so it has to be very robust, which implies less features
- It does not know how the system was configured so it cannot bring up everything
The end user application on the other hand is typically large and requires the system to be configured as desired by the end user before it can run.
The bootloader's job is to bridge the gap between the BootROM and the end user application.
Sometimes the bootloader process can be split into multiple stages, typically two.
2. Hardware Handoff
All Intel SoC FPGA projects start with a hardware project where various system settings that impact the HPS are entered by the user. These include:
- Pin multiplexing
- Pin settings
- SDRAM settings
- Clock settings
It is the bootloader's job to apply these settings and the process of the bootloader receiving these settings is called the hardware-to-software handoff.
Depending on the exact bootloader and SoC device family, the handoff can take various forms. Typically:
- For Cyclone V and Arria V SoCs, the handoff is a combination of XML files, binary files, and source code files, which are converted to source code and then compiled into the preloader
- For Intel Arria 10 SoCs, the handoff is contained in a single XML file that is converted to a device tree file and used by the bootloader
- For Intel Stratix 10 SoCs, the handoff information is part of the FPGA configuration bitstream
The primary method of entering or changing the handoff information is through editing them in the Qsys.
In addition to the handoff information, the bootloaders also have various settings that can be selected by the user through the following methods:
- Changing settings in the BSP editor
- Editing the bootloader source code
- Editing the bootloader device tree when a device tree is in use
Cyclone V Soc and Arria V SoC Handoff
Intel Arria 10 SoC Handoff
Intel Stratix 10 SoC Handoff
3. Available Bootloaders
Overview of Available Bootloaders
The following table lists the available bootloaders, types of licenses, supported SoCs, and availability of two-stage support:
U-Boot is a bootloader that is widely used by the industry and offers numerous capabilities:
- Optional first stage called "SPL" for systems with limited on-chip RAM (for example, Cyclone V SoC and Arria V SoC)
- Networking capability
- Flash memory support
- Command-line interface
- U-Boot custom applications
U-Boot is developed under a general-public licence (GPL) so any contributions that are made to a product that is being delivered to the public must also be made public.
The U-Boot source code is available at the U-Boot SoC FPGA page on the GitHub website.
For the Intel Arria 10 SoC, Arria V SoC, and Cyclone V SoC, the U-Boot source code is included with the Intel SoC FPGA Embedded Development Suite (SoC EDS), facilitating a simple and convenient development process.
Note that support for Cyclone V and Arria V SoCs was mainlined into the official U-Boot git tree on the GitHub website. Work is in progress to also mainline support for Intel Arria 10 SoCs.
The main generic U-Boot home page is located at the Das U-Boot -- the Universal Boot Loader web page.
The Minimal Preloader (MPL) is a bootloader developed using the Intel SoC FPGA Bare-metal Hardware Abstraction Libraries (HWLIBs). It is a single-stage bootloader designed for minimal footprint.
The MPL is available for the following devices:
- Cyclone V SoC
- Arria V SoC
- Intel Arria 10 SoC
The MPL is offered with a Berkeley Software Distribution (BSD) license, which allows more convenient development and deployment.
The MPL is delivered as part of the SoC EDS and is a project archive in the <SoC EDS Installation Folder>/embedded/examples/software/Intel® FPGA-SoCFPGA-HardwareLib-MPL.tar.gz file. The archive contains a file named README.txt, which contains detailed MPL descriptions and usage information.
The Unified Extensible Firmware Interface (UEFI) is a standardized firmware specification that simplifies platform initialization and firmware bootstrap.
The UEFI bootloader is available for the following devices:
- Intel Arria 10 SoC
- Intel Stratix 10 SoC
Because the UEFI is very well-specified and used by hundreds of technology companies, a lot of the code can be reused, enabling faster development cycles.
The UEFI as implemented on Intel SoC FPGAs comprises two different stages:
- Pre-Efi Initialization Phase (PEI). This stage configures the platform and loads either the end user application or DXE.
- Driver eXecution Environment (DXE). This stage loads additional UEFI drivers and allows more extended capabilities, such as networking and command-line interface.
The UEFI bootloader also offers the capability to run special applications that target the DXE environment. Such applications can be executed then upon exit control returns to the DXE.
UEFI is offered with a BSD license, which allows more convenient development and deployment.
The UEFI source code is available at the UEFI SoC FPGA page on the GitHub website.
For Intel Arria 10 SoCs, the UEFI is also delivered with SoC EDS enabling the same development flow as U-Boot.
The ARM Trusted Firmware (ATF) is a reference implementation of secure world software for ARMv8-a, implementing various ARM interface standards, such as Trusted Board Boot Requirements (TBBR) and Secure Monitor call.
The ATF is developed collaboratively under a BSD license, which allows convenient development and deployment.
The ATF has a small footprint, and is designed as a First Stage Bootloader (FSBL). It is used with UEFI to load the PXE then DXE, but it can also for example be used to load a simple bare-metal application.
The source code for Intel SoC FPGA port of ATF can be accessed at https://github.com/Intel FPGA-opensource/arm-trusted-firmware.
4. Getting Started
U-Boot Getting Started
The following resources are available for you to get started with U-Boot:
- Generating and Compiling Cyclone V Preloader
- Generating and Compiling Arria 10 U-Boot
MPL Getting Started
The MPL is delivered as part of the SoC EDS and is a project archive in the <SoC EDS Installation Folder>/embedded/examples/software/Intel FPGA-SoCFPGA-HardwareLib-MPL.tar.gz file. The archive contains a file named README.txt with detailed usage information for Intel Arria 10 SoCs, Arria V SoCs, and Cyclone V SoCs.
UEFI Getting Started
The following resources are available for you to get started with UEFI:
- Intel Arria 10 SoC UEFI Getting Started
- Intel Arria 10 SoC UEFI Boot Loader User Guide
- Intel Stratix 10 SoC UEFI Boot Loader User Guide
The following user guides are available:
Source code can be obtained from the following websites:
- Intel SoC FPGA U-Boot on GitHub
- Official Denx U-Boot Source Code
- Intel SoC FPGA UEFI on GitHub
- ARM Trusted Firmware on GitHub
- SoC EDS for Cyclone V, Arrial V and Arria 10 U-Boot source code and Arria 10 UEFI source code. The source code is generated by running the bsp-editor tool. See more details in SoC EDS User Guide, "Boot Tools User Guide" chapter.
- SoC EDS for S10 SoC U-Boot source code, in <SoC EDS Installation Folder>/embedded/host_tools/Intel FPGA/bootloaders/stratix10/u-boot/uboot-socfpga.tar.gz file.
- SoC EDS for MPL source code, located in the <SoC EDS Installation Folder>/embedded/examples/software/Intel FPGA-SoCFPGA-HardwareLib-MPL.tar.gz file.