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Ixiasoft
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Ixiasoft
3.4. Software Interface: Registers
This section provides information about the memory-mapped registers. You access these registers using the IP core control and status interface. The registers use 32-bit addresses; they are not byte addressable.
Write operations to a read-only register field have no effect. Read operations that address a Reserved register return an unspecified constant. Write operations to Reserved registers have no effect. Accesses to registers that do not exist in your IP core variation have an unspecified result.
The following tables list the memory mapped registers for the 40‑100GbE IP core and the memory mapped registers for the 40-100GbE IP core example design.
Word Offset |
Register Category |
---|---|
0x0–0x3F | PCS registers |
0x40–0x7F | Low Latency PHY IP core registers |
0x80–0xFF | 40GBASE-KR4 registers |
0x100 and above | 40-100GbE IP core MAC and example design registers |
Word Offset |
Register Description |
---|---|
0x000–0x009 |
Transceiver PHY control and status registers. Some of these registers are available only for Stratix IV devices. These registers are not the Altera transceiver PHY IP core registers. |
0x00A–0x00F |
Reserved. |
0x010–0x014 |
Lock status registers. |
0x015–0x016 |
Bit error flag registers. |
0x017 |
PCS hardware error register. |
0x018 |
BER monitor register. |
0x019 |
Test mode register. |
0x01A |
Test pattern counter register. |
0x01B |
One of two link fault signaling registers. |
0x01C |
Reserved. |
0x01D |
PHY reset register. |
0x01E–0x01F |
Reserved. |
0x020–0x023 |
PCS‑VLANE registers. |
0x024–0x02F |
Reserved. |
0x030–0x032 |
PRBS registers. |
0x033–0x03F |
Reserved. |
0x040–0x07F (Stratix IV only) |
Reserved. |
0x040–0x07F (Arria V GZ and Stratix V) |
For all options except the CAUI-4 configuration: Maps to word addresses 0x040-0x07F in the Low Latency PHY IP core register map. For the CAUI-4 configuration only : Reserved. |
0x080–0x0FF |
Reserved in non-40GBASE-KR4 IP core variations. |
0x080–0x0AF |
Reserved in 40GBASE-KR4 IP core variations. |
0x0B0–0x0BD |
40GBASE-KR4 top-level and FEC registers. |
0x0BE–0x0BF |
Reserved. |
0x0C0–0x0CC |
40GBASE-KR4 auto-negotiation registers. |
0x0CD–0x0CF |
Reserved. |
0x0D0–0x0EB |
40GBASE-KR4 link training registers. |
0x0EC–0x0FF |
Reserved. |
0x100–0x103 |
MAC configuration and filter registers. |
0x104–0x10F |
Reserved. |
0x110–0x117 |
Pause registers. |
0x118–0x11F |
Reserved. |
0x120 |
MAC hardware error register. |
0x121 |
MAC reset register. |
0x122 |
One of two link fault signaling registers. |
0x123 |
CRC configuration register. |
0x124 |
Padding configuration register. One of the MAC feature configuration registers. |
0x125 |
Preamble pass-through configuration register. One of the MAC feature configuration registers. |
0x126–0x127 |
IPG adjustment registers. Two of the MAC feature configuration registers. |
0x140–0x17F |
MAC address registers. |
0x180–0x1FF |
Reserved. |
0x200–0x229 |
Transmit side statistics registers that are not TX packet statistics registers. |
0x22A–0x22D |
TX Packet Statistics. |
0x22E–0x27F |
Reserved. |
0x280–0x2A9 |
Receive side statistics registers that are not RX packet statistics registers. |
0x2AA–0x2B8 |
RX packet statistics registers. |
0x2B9–0x3FF |
Reserved. |
0x400–0x423 |
40-100GbE example design registers. Refer to the following table. |
0x800-0x9FF |
Altera’s Low Latency PHY IP core registers, for use with the CAUI-4 configuration only. Offsets 0x800-0x9FF are for CAUI-4 lane 1, offsets 0xA00-0xBFF are for CAUI-4 lane 2, offsets 0xC00-0xDFF are for CAUI-4 lane 3, and offsets 0xE00-0xFFF are for CAUI-4 lane 4. Each lane maps to word addresses 0x000-0x1FF for one low latency PHY transceiver channel. |
0xA00-0xBFF |
|
0xC00-0xDFF |
|
0xE00-0xFFF |
Word Offset |
Register Category |
---|---|
0x400–0x403 |
PMD registers |
0x404–0xF0F |
Reserved |
0x410–0x413 |
MDIO registers |
0x414–0x41F |
Reserved |
0x420–0x423 |
2‑wire serial interface registers |