Intel® High Level Synthesis Accelerator Functional Unit Design Example User Guide

Download PDF
ID 683025
Date 7/19/2019
Public
Document Table of Contents
Document Table of Contents x
1. About the HLS AFU Design Example 2. Building the HLS AFU Design Example 3. Customizing the HLS AFU 4. HLS AFU Design Example Description 5. Troubleshooting HLS AFU Designs 6. Document Revision History for the HLS AFU Design Example User Guide
1. About the HLS AFU Design Example x
1.1. HLS AFU Design Example Files 1.2. Acronyms in the HLS AFU Design Example User Guide
2. Building the HLS AFU Design Example x
2.1. HLS AFU Design Example Software Requirements 2.2. Compiling and Simulating the HLS Component with the i++ Command 2.3. Generating a Platform Designer Container for the HLS Component 2.4. Generating the ASE Testbench 2.5. Running the ASE Testbench 2.6. Compiling the AF Bitstream 2.7. Loading AF Bitstream and Running the Host Application
3. Customizing the HLS AFU x
3.1. Acceleration Stack Configuration Files
4. HLS AFU Design Example Description x
4.1. AFU Description 4.2. Host Application Description
4.1. AFU Description x
4.1.1. HLS AFU Container
4.1.1. HLS AFU Container x
4.1.1.1. HLS AFU Avalon-MM I/O Slave Interface 4.1.1.2. HLS AFU Avalon-MM Master Interfaces
5. Troubleshooting HLS AFU Designs x
5.1. Platform Designer Opens with an Error 5.2. The design unit was not found Error When Running the make sim Command 5.3. Verilog HDL Compilation Errors 5.4. Compilation Errors During ASE Testbench Generation 5.5. Incorrect Output During Simulation 5.6. AF Bitstream Compilation Fails 5.7. Verilog Files Not Found Errors
1. About the HLS AFU Design Example
2. Building the HLS AFU Design Example
3. Customizing the HLS AFU
4. HLS AFU Design Example Description
5. Troubleshooting HLS AFU Designs
6. Document Revision History for the HLS AFU Design Example User Guide

2.6. Compiling the AF Bitstream

Compiling a bitstream takes significantly longer than simulating the AFU. The AFU is compiled with Intel® Quartus® Prime to generate an FPGA bitstream. is generated.

Before you compile the AF bitstream, ensure that you have complete the steps in Generating a Platform Designer Container for the HLS Component.

Refer to hls_afu/setup_gbs.sh to automate these steps.

To compile the AF bitstream:

Generate the AF build environment and create the AF (.gbs) image.
This process takes approximately 30 minutes. 
$ afu_synth_setup --source hw/rtl/filelist.txt build_synth 
$ cd build_synth
$ $OPAE_PLATFORM_ROOT/bin/run.sh

When the AF is created successfully, you get the following message:

Wrote hls_afu.gbs

===========================================================================
 PR AFU compilation complete
 AFU gbs file is 'hls_afu.gbs'
===========================================================================
Level Two Title