Intel® Cyclone® 10 GX Transceiver PHY User Guide

ID 683054
Date 4/14/2023
Public
Document Table of Contents

2.9.2. Using the Basic/Custom, Basic/Custom with Rate Match Configurations of Standard PCS

Use one of the following transceiver configuration rules to implement protocols such as SONET/SDH, SDI/HD, SATA, or your own custom protocol:

  • Basic protocol
  • Basic protocol with low latency enabled
  • Basic with rate match protocol
Figure 83. Transceiver Channel Datapath and Clocking for the Basic and Basic with Rate Match ConfigurationsThe clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width is 10 bits.


In low latency modes, the transmitter and receiver FIFOs are always enabled. Depending on the targeted data rate, you can optionally bypass the byte serializer and deserializer blocks.

Figure 84. Transceiver Channel Datapath and Clocking for Basic Configuration with Low Latency EnabledThe clocking calculations in this figure are for an example when the data rate is 1250 Mbps and the PMA width is 10 bits.


In low latency modes, the transmitter and receiver FIFOs are always enabled. Depending on the targeted data rate, you can optionally bypass the byte serializer and deserializer blocks.