Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon Streaming Hard IP for PCIe* Design Example User Guide

Download PDF
ID 683065
Date 1/13/2022
Public
Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description A. Document Revision History for Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® streaming Hard IP for PCIe* Design Example User Guide
1. Quick Start Guide x
1.1. Directory Structure 1.2. Design Components 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design in Hardware
2. Design Example Description x
2.1. Functional Description 2.2. Creating a Signal Tap Debug File to Match Your Design Hierarchy 2.3. Intel® Arria® 10 Development Kit Conduit Interface 2.4. Serial Data Signals 2.5. Registers
1. Quick Start Guide
2. Design Example Description
A. Document Revision History for Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon® streaming Hard IP for PCIe* Design Example User Guide

2.5. Registers

There are no control registers for the PIO design example. The PCI Express Base Specification 3.0 defines a comprehensive set of configuration, control, and status registers to control and debug the design example.

Related Information
Level Two Title