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1.1. List of Abbreviations
1.2. Introduction
1.3. Intel® Stratix® 10 Early Power Estimator Tool (EPE)
1.4. Intel® Stratix® 10 FPGA Package Physical Design
1.5. Physical Package Structure
1.6. Intel® Stratix® 10 FPGA Thermal Design Parameters
1.7. Intel® Stratix® 10 Compact Thermal Model (CTM)
1.8. Intel® Stratix® 10 Temperature Sensing Diodes (TSD)
1.9. Intel® Stratix® 10 Thermal Design Process
1.10. Early Power Estimator (EPE)
1.11. Transceiver Channel Spreading
1.12. Thermal Parameter Dependencies
1.13. Intel® Stratix® 10 Thermal Design Example
1.14. Document Revision History for AN 787: Intel® Stratix® 10 Thermal Modeling and Management with the Early Power Estimator
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1.13.4. TSD offset Assessment for the Example
As indicated previously the temperature sensors are not always in the exact position of the hot spots on the transceivers and depending on the transceiver placement, the EPE calculates the offset value which needs to be added to the field reading.
The transceiver TSDs in the first example should report the following values:
TSD_HSSI_2_0 = 85.5 °C
TSD_HSSI_0_0 = 85.5 °C
TSD_HSSI_2_1 = 81.2 °C
TSD_HSSI_0_1 = 80 °C
Adding the offset values to these numbers provide the actual temperatures shown below:
TJ _HSSI_2_0= 85.5+8 = 93.8 °C
TJ _HSSI_0_0= 85.5+5 = 90.5 °C
TJ _HSSI_2_1=81.2+7 = 88.2 °C
TJ _HSSI_0_1=80+10 = 90 °C
Note: The TSDs have an accuracy of ±5 °C; therefore, the reported temperature can be off by 5 °C. In order not to exceed the operating temperature, Intel recommends building a 5 °C margin to the thermal design.