JESD204B Intel® Arria® 10 FPGA IP Design Example User Guide

ID 683113
Date 10/14/2022
Public
Document Table of Contents

1.2.6. Simulation

Note: The simulation flow is only supported for System Console Control design example only. The simulation flow is not supported for Nios® Control design example.

Execute the simulation by running the relevant simulation run scripts in the supported simulator environment. The following table shows the simulators supported along with the relevant run scripts.

Table 15.  Supported Simulators
Simulators Simulation Directory Run Script
Riviera-PRO* /testbench/aldec/ run_tb_top.tcl
ModelSim* /testbench/mentor/ run_tb_top.tcl
QuestaSim*
VCS* /testbench/synopsys/vcs/ run_tb_top.sh
VCS* MX /testbench/synopsys/vcsmx/ run_tb_top.sh
Xcelium* /testbench/xcelium/ run_tb_top.sh

The design generates the simulation results which include the transcript or log files in the relevant simulation directory.