High-speed Reed-Solomon IP Core User Guide

Download PDF
ID 683120
Date 11/06/2017
Public
Document Table of Contents
Document Table of Contents x
1. About the High-speed Reed-Solomon IP Core 2. High-speed Reed-Solomon IP Core Getting Started 3. High-speed Reed-Solomon IP Core Functional Description 4. High-speed Reed-Solomon IP Core User Guide Document Revision History A. High-Speed Reed-Solomon IP Core Document Archive
1. About the High-speed Reed-Solomon IP Core x
1.1. Reed-Solomon II versus High-Speed Reed Solomon Intel® FPGA IP 1.2. High-speed Reed-Solomon IP Core Features 1.3. High-Speed Reed-Solomon IP Device Family Support 1.4. DSP IP Core Verification 1.5. High-speed Reed-Solomon IP Core Release Information 1.6. High-speed Reed-Solomon IP Core Performance and Resource Utilization
2. High-speed Reed-Solomon IP Core Getting Started x
2.1. Installing and Licensing Intel® FPGA IP Cores 2.2. IP Catalog and Parameter Editor 2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) 2.4. Simulating Intel® FPGA IP Cores
2.1. Installing and Licensing Intel® FPGA IP Cores x
2.1.1. Intel® FPGA IP Evaluation Mode 2.1.2. High-speed Reed-Solomon IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
2.3. Generating IP Cores ( Intel® Quartus® Prime Pro Edition) x
2.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
3. High-speed Reed-Solomon IP Core Functional Description x
3.1. High-Speed Reed-Solomon Architecture 3.2. High-Speed Reed-Solomon IP Core Parameters 3.3. High-speed Reed-Solomon IP Core Interfaces and Signals
3.1. High-Speed Reed-Solomon Architecture x
3.1.1. High-Speed Reed-Solomon Encoder 3.1.2. High-Speed Reed-Solomon Decoder
3.3. High-speed Reed-Solomon IP Core Interfaces and Signals x
Avalon-ST Interfaces 3.3.1. High-speed Reed-Solomon IP Core Signals
1. About the High-speed Reed-Solomon IP Core
2. High-speed Reed-Solomon IP Core Getting Started
3. High-speed Reed-Solomon IP Core Functional Description
4. High-speed Reed-Solomon IP Core User Guide Document Revision History
A. High-Speed Reed-Solomon IP Core Document Archive

3.3. High-speed Reed-Solomon IP Core Interfaces and Signals

The ready latency on the Avalon-ST input interface is 0; the number of symbols per beat is fixed to 1. The latency of the decoder is N/P+ (BM speed x R) + 10; the latency of the encoder is 6.

The clock and reset interfaces drive or receive the clock and reset signal to synchronize the Avalon-ST interfaces and provide reset connectivity. The status interface is a conduit interface that consists of three error status signals for a codeword. The decoder obtains the error symbol value, number of error symbols, and number of error bits in a codeword from the status signals.

Avalon-ST Interfaces

Avalon-ST interfaces define a standard, flexible, and modular protocol for data transfers from a source interface to a sink interface.

The input interface is an Avalon-ST sink and the output interface is an Avalon-ST source.

Avalon-ST interface signals can describe traditional streaming interfaces supporting a single stream of data without knowledge of channels or packet boundaries. Such interfaces typically contain data, ready, and valid signals.

Avalon-ST interfaces support backpressure, which is a flow control mechanism where a sink can indicate to a source to stop sending data. The sink typically uses backpressure to stop the flow of data when its FIFO buffers are full or when it has congestion on its output.


Section Content
High-speed Reed-Solomon IP Core Signals

Level Two Title