Intel® Agilex™ SEU Mitigation User Guide

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ID 683128
Date 12/30/2022
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Document Table of Contents
Document Table of Contents x
1. Intel® Agilex™ SEU Mitigation Overview 2. Intel® Agilex™ CRAM Error Mitigation 3. Secure Device Manager ECC and SmartVID Errors Detection 4. Intel® Agilex™ SEU Mitigation Implementation Guides 5. IP and Software References 6. Intel® Agilex™ SEU Mitigation User Guide Archives 7. Document Revision History for the Intel® Agilex™ SEU Mitigation User Guide
1. Intel® Agilex™ SEU Mitigation Overview x
1.1. SEU Mitigation Techniques 1.2. Configuration RAM 1.3. Memory Blocks 1.4. Secure Device Manager ECC and SmartVID 1.5. Triple Modular Redundancy 1.6. Failure Rates
2. Intel® Agilex™ CRAM Error Mitigation x
2.1. CRAM Error Detection and Correction 2.2. Error Message Queue 2.3. Scrubbing 2.4. SEU Sensitivity Processing 2.5. Design Hierarchy Sensitivity Classification 2.6. Evaluation of System Response to Upsets
2.4. SEU Sensitivity Processing x
2.4.1. Advanced SEU Detection Intel® FPGA IP
2.4.1. Advanced SEU Detection Intel® FPGA IP x
2.4.1.1. Release Information for Advanced SEU Detection Intel® FPGA IP 2.4.1.2. On-Chip Lookup Sensitivity Processing 2.4.1.3. Off-Chip Lookup Sensitivity Processing 2.4.1.4. Sensitivity Map Header Lookup
2.5. Design Hierarchy Sensitivity Classification x
2.5.1. Hierarchy Tagging
2.6. Evaluation of System Response to Upsets x
2.6.1. Fault Injection Debugger
3. Secure Device Manager ECC and SmartVID Errors Detection x
3.1. SDM ECC Error Message Bits 3.2. SmartVID Error Message Bits 3.3. SDM ECC and SmartVID Errors Signals Behavior
4. Intel® Agilex™ SEU Mitigation Implementation Guides x
4.1. Setting the SEU_ERROR Pin 4.2. Setting Up the SEU Mitigation Features 4.3. Enabling Priority Scrubbing 4.4. Assigning Regions for Hierarchy Tagging 4.5. Sensitivity Map Header 4.6. Using the Fault Injection Debugger
4.5. Sensitivity Map Header x
4.5.1. Programming the .smh File into Memory 4.5.2. Looking up the Sensitivity Map Header
4.5.2. Looking up the Sensitivity Map Header x
4.5.2.1. Sensitivity Map Header Revision 4 File Format Reference
4.6. Using the Fault Injection Debugger x
4.6.1. Launching and Setting Up the Fault Injection Debugger 4.6.2. Configuring Your Device using a Software Object File (.sof) 4.6.3. Constraining Regions for Fault Injection 4.6.4. Injecting Errors to Random Locations 4.6.5. Injecting Errors to Specific Locations 4.6.6. Injecting Double Adjacent Errors 4.6.7. Injecting SDM ECC Errors 4.6.8. Analyzing SEU or SDM ECC Errors Using Signal Tap
4.6.6. Injecting Double Adjacent Errors x
4.6.6.1. Injecting Double Adjacent Errors: Command-Line Interface 4.6.6.2. Injecting Double Adjacent Errors: GUI
4.6.7. Injecting SDM ECC Errors x
4.6.7.1. Injecting SDM ECC Errors: Command-Line Interface 4.6.7.2. Injecting SDM ECC Errors: GUI
5. IP and Software References x
5.1. Advanced SEU Detection Intel® FPGA IP References 5.2. Fault Injection Debugger Software References
5.1. Advanced SEU Detection Intel® FPGA IP References x
5.1.1. Advanced SEU Detection Intel® FPGA IP Parameter Settings 5.1.2. Advanced SEU Detection IP Core Ports
5.2. Fault Injection Debugger Software References x
5.2.1. Fault Injection Debugger GUI Tool 5.2.2. Fault Injection Debugger Command-Line Interface
1. Intel® Agilex™ SEU Mitigation Overview
2. Intel® Agilex™ CRAM Error Mitigation
3. Secure Device Manager ECC and SmartVID Errors Detection
4. Intel® Agilex™ SEU Mitigation Implementation Guides
5. IP and Software References
6. Intel® Agilex™ SEU Mitigation User Guide Archives
7. Document Revision History for the Intel® Agilex™ SEU Mitigation User Guide

4.3. Enabling Priority Scrubbing

To specify areas for high priority internal scrubbing, use the Intel® Quartus® Prime Logic Lock region and design partition features.
  1. Open the Chip Planner and Design Partition Planner.
    1. Click Tools > Design Partition Planner
    2. Click Tools > Chip Planner
  2. In the Chip Planner window, go to the Tasks pane, and double-click Report Design Partitions. The Report Design Partitions task causes the Chip Planner to display the physical location of design entities using the same colors that the entities are displayed in the Design Partition Planner.
  3. In the Design Partition Planner window, drag the entities of interest (entities to be included in the priority scrubbing area) out from their parents. Alternatively, you can right click the entity of interest and click Extract from Parent.
  4. Create a partition for each of the entity of interest by right-clicking the entity, and clicking Create Design Partition.
  5. Create a Logic Lock region for each partition by right-clicking the partition and clicking Create Logic Lock Region. Alternatively, you can create a Logic Lock region using the Logic Lock Region window from the Intel® Quartus® Prime menu, Assignments > Logic Lock Regions Window. You can specify the size of the Logic Lock Region by changing the values in Width and Height accordingly. The number of priority SEU sectors depend on the area covered by the Width and Height setting.
  6. From the Intel® Quartus® Prime menu, select Assignments > Assignment Editor.
  7. In the Assignment Editor window, assign Priority SEU Area to the design partition where you place the Logic Lock region. Select On for Value and Yes for Enabled.
    Alternatively, you can include the following instruction in the project's Intel® Quartus® Prime settings file (.qsf): 
    set_instance_assignment -name PRIORITY_SEU_AREA ON -to <partition name>
  8. Compile the design once all the settings are completed.

The Intel® Quartus® Prime software sets the internal scrubbing schedule of the priority sectors to "as fast as possible". The internal scrubbing schedule for other sectors follows the project's Minimum SEU interval global assignment.

With priority scrubbing enabled, the Quartus System Message window reports the summary of sectors for the priority scrubbing and non-priority scrubbing when you load your *.sof file in Quartus Programmer. This includes number of sectors, groups, and the minimum SEU interval.

Figure 8. Example of Quartus System Message with Priority and Regular SEU info
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