F-Tile Avalon® Streaming Intel® FPGA IP for PCI Express* User Guide

ID 683140
Date 4/04/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

3.3. Avalon-ST TX/RX

The Avalon-ST IP for PCI Express pairs with F-Tile. Within F-tile, FGT PHY (Transceiver) interacts with PCI Express Hard IP (HIP) directly. PCI Express Soft IP (within FPGA fabric) interacts with PCI Express Hard IP via MAIB-AIB interface. (EMIB).