AN 584: Timing Closure Methodology for Advanced FPGA Designs

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ID 683145
Date 10/08/2021
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Document Table of Contents
Document Table of Contents x
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs x
1.1. Plan Early for Timing Closure 1.2. Customize Settings Per Application 1.3. Change Fitter Placement Seeds 1.4. Planning for Timing Closure 1.5. Best Practices for Timing Closure 1.6. Resolving Common Timing Issues 1.7. Conclusion 1.8. Document Revision History for AN 584: Timing Closure Methodology for Advanced FPGA Designs
1.4. Planning for Timing Closure x
1.4.1. Timing Closure Planning at Specification Stage 1.4.2. Timing Closure Planning at Coding and Compilation Stage
1.4.1. Timing Closure Planning at Specification Stage x
1.4.1.1. Plan for the Target FPGA Device 1.4.1.2. Plan for On-Chip Debugging
1.4.2. Timing Closure Planning at Coding and Compilation Stage x
1.4.2.1. Plan for Design Hierarchy and Block Partitioning 1.4.2.2. Plan for Early Compilation of Design Blocks 1.4.2.3. Plan for Verification
1.5. Best Practices for Timing Closure x
1.5.1. Performance Planning General Guidelines 1.5.2. Follow Synchronous Design Practices 1.5.3. Follow Recommended Coding Styles 1.5.4. Constraining and Compiling Your Design
1.5.4. Constraining and Compiling Your Design x
1.5.4.1. Setting Location Constraints 1.5.4.2. Setting Proper Timing Constraints 1.5.4.3. Using Optimal Compiler Settings for Your Design
1.6. Resolving Common Timing Issues x
1.6.1. Excessive Logic Levels 1.6.2. Improper Timing Constraints 1.6.3. Handling High Fan-Out Registers 1.6.4. Metastability Issues 1.6.5. Reset Signal Related Issues 1.6.6. Small Margin Timing Constraint Failures 1.6.7. Long Compilation Times
1.6.2. Improper Timing Constraints x
1.6.2.1. Check Constraint Diagnostics
1.6.4. Metastability Issues x
1.6.4.1. Check CDC Design Assistant Rule Violations 1.6.4.2. Check CDC Report
1.6.5. Reset Signal Related Issues x
1.6.5.1. Recovery and Removal Issues
1. AN 584: Timing Closure Methodology for Advanced FPGA Designs

1.6.3. Handling High Fan-Out Registers

Wide distribution of registers is one of the main causes of excess delay on timing paths.

You can use the Chip Planner to view the location of high fan-out registers and the locations they are driving. In most circumstances, the Fitter placement of registers is superior to manual placement.

For more information about the Chip Planner, refer to Analyzing and Optimizing the Design Floorplan in Intel® Quartus® Prime Pro Edition User Guide: Design Optimization.

High fan-out registers, such as broadcast signals driving multiple blocks, placed in different directions, can have placement-warping effects on the floorplan that impact maximum clock speed. You can identify high fan-out registers by clicking Tasks > Reports > Design Metrics > Report Register Spread.

Figure 8. Report Register Spread

The report shows the list of possible registers being pulled by sink registers in various directions. To learn more about this report, refer to Report Register Spread in Intel® Quartus® Prime Pro Edition User Guide: Design Optimization.

You can correct this problem by duplicating the register using the DUPLICATE_REGISTER or DUPLICATE_HIERARCHY_DEPTH .qsf assignment.

Alternatively, you can manually modify the RTL to implement the duplication, but you must also add the preserve_syn_only synthesis attributes to the duplicates to preserve the nodes through synthesis. The attribute allows the Fitter to do retiming or other optimizations if needed. 

logic dup_reg /* synthesis preserve_syn_only */;
(*preserve_syn_only*) logic dup_reg;

For more information on register duplication commands and techniques, refer to Duplicate Registers for Fan-Out Control in Intel® Quartus® Prime Pro Edition User Guide: Design Optimization.

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