Intel® Stratix® 10 Device Datasheet

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ID 683181
Date 12/08/2023
Public
Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Device Datasheet
Intel® Stratix® 10 Device Datasheet x
Electrical Characteristics Switching Characteristics Configuration Specifications I/O Timing Programmable IOE Delay Glossary Document Revision History for the Intel® Stratix® 10 Device Datasheet
Electrical Characteristics x
Operating Conditions
Operating Conditions x
Absolute Maximum Ratings Maximum Allowed Overshoot and Undershoot Voltage Recommended Operating Conditions DC Characteristics I/O Standard Specifications
Recommended Operating Conditions x
Recommended Operating Conditions Transceiver Power Supply Operating Conditions HPS Power Supply Operating Conditions
DC Characteristics x
Supply Current and Power Consumption I/O Pin Leakage Current Bus Hold Specifications OCT Calibration Accuracy Specifications OCT Without Calibration Resistance Tolerance Specifications Pin Capacitance Internal Weak Pull-Up Resistor
I/O Standard Specifications x
Single-Ended I/O Standards Specifications Single-Ended SSTL, HSTL, and HSUL I/O Reference Voltage Specifications Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications Differential SSTL I/O Standards Specifications Differential HSTL and HSUL I/O Standards Specifications Differential I/O Standards Specifications
Single-Ended SSTL, HSTL, and HSUL I/O Standards Signal Specifications x
Differential POD12 Standards Specifications
Switching Characteristics x
Core Performance Specifications Periphery Performance Specifications L-Tile Transceiver Performance Specifications H-Tile Transceiver Performance Specifications E-Tile Transceiver Performance Specifications P-Tile Transceiver Performance Specifications HPS Performance Specifications
Core Performance Specifications x
Clock Tree Specifications PLL Specifications DSP Block Specifications Memory Block Specifications Direct Interface Bus (DIB) Specifications Internal Temperature Sensing Diode Specifications External Temperature Sensing Diode Specifications Internal Voltage Sensor Specifications
PLL Specifications x
Fractional PLL Specifications I/O PLL Specifications
Periphery Performance Specifications x
High-Speed I/O Specifications DPA Lock Time Specifications LVDS Soft-CDR/DPA Sinusoidal Jitter Tolerance Specifications Memory Standards Supported by the Hard Memory Controller Memory Standards Supported by the Soft Memory Controller Memory Standards Supported by the HPS Hard Memory Controller DLL Range Specifications Memory Output Clock Jitter Specifications Performance Specifications of the HBM2 Interface in Intel® Stratix® 10 MX, NX, and DX 2100 Devices HBM2 Interface Performance OCT Calibration Block Specifications
L-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 L-Tile Devices Transceiver Specifications for Intel® Stratix® 10 L-Tile Devices
H-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 H-Tile Devices Transceiver Specifications for Intel® Stratix® 10 H-Tile Devices
E-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 E-Tile Devices Transceiver Reference Clock Specifications Transmitter Specifications for Intel® Stratix® 10 E-Tile Devices Receiver Specifications for Intel® Stratix® 10 E-Tile Devices
P-Tile Transceiver Performance Specifications x
Transceiver Performance for Intel® Stratix® 10 DX P-Tile Devices Transceiver Reference Clock Specifications Transmitter Specification for Intel® Stratix® 10 DX P-Tile Devices Receiver Specifications for Intel® Stratix® 10 DX P-Tile Devices
HPS Performance Specifications x
HPS Clock Performance HPS Internal Oscillator Frequency HPS PLL Specifications HPS Cold Reset HPS SPI Timing Characteristics HPS SD/MMC Timing Characteristics HPS USB UPLI Timing Characteristics HPS Ethernet Media Access Controller (EMAC) Timing Characteristics HPS I2C Timing Characteristics HPS NAND Timing Characteristics HPS Trace Timing Characteristics HPS GPIO Interface HPS JTAG Timing Characteristics HPS Programmable I/O Timing Characteristics
HPS PLL Specifications x
HPS PLL Input Requirements HPS PLL Performance
Configuration Specifications x
General Configuration Timing Specifications POR Specifications External Configuration Clock Source Requirements JTAG Configuration Timing AS Configuration Timing Avalon® -ST Configuration Timing Configuration Bit Stream Sizes
Intel® Stratix® 10 Device Datasheet

I/O PLL Specifications

Table 30.  I/O PLL Specifications for Intel® Stratix® 10 Devices
Symbol Parameter Condition Min Typ Max Unit
fIN Input clock frequency –1 speed grade 10 — 1,100 47 MHz
–2 speed grade 10 — 900 47 MHz
–3 speed grade 10 — 750 47 MHz
fINPFD Input clock frequency to the PFD — 10 — 325 MHz
fVCO PLL VCO operating range –1 speed grade 600 — 1,600 MHz
–2 speed grade 600 — 1,434 MHz
–3 speed grade 600 — 1,280 48 MHz
fCLBW PLL closed-loop bandwidth — 0.5 — 10 MHz
tEINDUTY Input clock or external feedback clock input duty cycle — 40 — 60 %
fOUT Output frequency for internal clock (C counter) –1 speed grade — — 1,100 MHz
–2 speed grade — — 900 MHz
–3 speed grade — — 750 MHz
fOUT_EXT Output frequency for external clock output –1 speed grade — — 800 MHz
–2 speed grade — — 720 MHz
–3 speed grade — — 650 MHz
tOUTDUTY Duty cycle for dedicated external clock output (when set to 50%) — 45 50 55 %
tFCOMP External feedback clock compensation time — — — 5 ns
fDYCONFIGCLK Dynamic configuration clock for mgmt_clk and scanclk — — — 200 MHz
tLOCK Time required to lock from end-of-device configuration or deassertion of areset — — — 1 ms
tDLOCK Time required to lock dynamically (after switchover or reconfiguring any non-post-scale counters/delays) — — — 1 ms
tPLL_PSERR Accuracy of PLL phase shift — — — ±50 ps
tARESET Minimum pulse width on the areset signal — 10 — — ns
tINCCJ 49 50 Input clock cycle-to-cycle jitter FREF ≥ 100 MHz — — 0.15 UI (p-p)
FREF < 100 MHz — — ±750 ps (p-p)
tOUTPJ_DC Period jitter for dedicated clock output FOUT ≥ 100 MHz — — 175 ps (p-p)
FOUT < 100 MHz — — 17.5 mUI (p-p)
tOUTCCJ_DC Cycle-to-cycle jitter for dedicated clock output FOUT ≥ 100 MHz — — 175 ps (p-p)
FOUT < 100 MHz — — 17.5 mUI (p-p)
tOUTPJ_IO 51 Period jitter for clock output on the regular I/O FOUT ≥ 100 MHz — — 600 ps (p-p)
FOUT < 100 MHz — — 60 mUI (p-p)
tOUTCCJ_IO 51 Cycle-to-cycle jitter for clock output on the regular I/O FOUT ≥ 100 MHz — — 600 ps (p-p)
FOUT < 100 MHz — — 60 mUI (p-p)
tCASC_OUTPJ_DC Period jitter for dedicated clock output in cascaded PLLs through dedicated cascade path and core clock fabric FOUT ≥ 100 MHz — — 175 ps (p-p)
FOUT < 100 MHz — — 17.5 mUI (p-p)
Related Information
47 This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is dependent on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
48 This specification is only applicable when the I/O PLL is instantiated with the IOPLL Intel® FPGA IP core. For I/O PLL instantiated with LVDS SERDES Intel® FPGA IP core, PHY Lite for Parallel Interfaces Intel Stratix 10 FPGA IP core, External Memory Interfaces Intel Stratix 10 FPGA IP core, and High Bandwidth Memory (HBM-2) Interface Intel® FPGA IP core, the maximum fVCO is 1,250 MHz.
49  A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source with jitter < 120 ps.
50 FREF is fIN/N, specification applies when N = 1.
51 External memory interface clock output jitter specifications use a different measurement method, which are available in Memory Output Clock Jitter Specifications for Intel® Stratix® 10 Devices table.
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