Intel® SoC FPGA Embedded Development Suite (SoC EDS) User Guide

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ID 683187
Date 3/12/2021
Public
Document Table of Contents
Document Table of Contents x
1. Introduction to the Intel® SoC FPGA Embedded Development Suite (SoC EDS) 2. Installing the Tools 3. Running the Tools 4. SoC EDS Licensing 5. Arm* Development Studio* for Intel® SoC FPGA Edition 6. Boot Tools User Guide 7. Hardware Library 8. Using the HPS Flash Programmer 9. Bare Metal Compilers 10. SD Card Boot Utility 11. Linux* Device Tree Generator 12. Support and Feedback
1. Introduction to the Intel® SoC FPGA Embedded Development Suite (SoC EDS) x
1.1. Notice 1.2. Tool Versions 1.3. Differences Between Standard and Professional Editions 1.4. Overview 1.5. Hardware and Software Development Roles 1.6. Hardware – Software Development Flow 1.7. Introduction to the Intel® SoC FPGA EDS Revision History
1.5. Hardware and Software Development Roles x
1.5.1. Hardware Engineer 1.5.2. Bare Metal and RTOS Developer 1.5.3. Linux* Kernel and Driver Developer 1.5.4. Linux* Application Developer
2. Installing the Tools x
2.1. Installation Folders 2.2. Linux 2.3. Windows 2.4. Installing the Intel® SoC FPGA EDS Document Revision History
2.2. Linux x
2.2.1. Installing SoC EDS 2.2.2. Installing Arm* DS* 2.2.3. Installing Linaro* Bare Metal Toolchain
2.3. Windows x
2.3.1. Installing SoC EDS 2.3.2. Installing Arm* DS* 2.3.3. Installing Cygwin 2.3.4. Installing MinGW 2.3.5. Installing Linaro* Bare Metal Toolchain
3. Running the Tools x
3.1. Linux* 3.2. Windows* 3.3. Running the Tools Revision History
4. SoC EDS Licensing x
4.1. Getting the License 4.2. Activating the License 4.3. Intel® SoC FPGA EDS Licensing Revision History
5. Arm* Development Studio* for Intel® SoC FPGA Edition x
5.1. Arm* DS* for Intel® SoC FPGA Edition Revision History
6. Boot Tools User Guide x
6.1. Introduction 6.2. BSP Generator 6.3. Bootloader Image Tool (mkpimage) 6.4. U-Boot Image Tool (mkimage) 6.5. Building the Bootloader 6.6. Boot Tools User Guide Revision History
6.2. BSP Generator x
6.2.1. BSP Generation Flow 6.2.2. BSP Generator Graphical User Interface 6.2.3. BSP Generator Command Line Interface 6.2.4. BSP Files and Folders 6.2.5. BSP Settings
6.2.1. BSP Generation Flow x
6.2.1.1. Cyclone® V SoC and Arria® V SoC Flow 6.2.1.2. Intel® Arria® 10 SoC Flow
6.2.3. BSP Generator Command Line Interface x
6.2.3.1. bsp-create-settings
6.3. Bootloader Image Tool (mkpimage) x
6.3.1. Operation 6.3.2. Header File Format 6.3.3. Tool Usage 6.3.4. Output Image Layout
6.3.4. Output Image Layout x
6.3.4.1. Base Address 6.3.4.2. Size 6.3.4.3. Address Alignment 6.3.4.4. Padding
6.3.4.3. Address Alignment x
6.3.4.3.1. NAND Flash 6.3.4.3.2. Serial NOR Flash 6.3.4.3.3. SD/MMC
6.4. U-Boot Image Tool (mkimage) x
6.4.1. Tool Options 6.4.2. Usage Examples
6.5. Building the Bootloader x
6.5.1. Building the Cyclone® V SoC and Arria® V SoC Preloader 6.5.2. Building the Intel® Arria® 10 SoC Bootloader 6.5.3. Building the Intel® Stratix® 10 SoC and Intel® Agilex™ Devices
7. Hardware Library x
7.1. Feature Description 7.2. Hardware Library Reference Documentation 7.3. System Memory Map 7.4. Hardware Library Revision History
7.1. Feature Description x
7.1.1. SoC Abstraction Layer (SoCAL) 7.1.2. HW Manager
8. Using the HPS Flash Programmer x
8.1. HPS Flash Programmer Command-Line Utility 8.2. How the HPS Flash Programmer Works 8.3. Using the Flash Programmer from the Command Line 8.4. Supported Memory Devices 8.5. HPS Flash Programmer User Guide Revision History
8.3. Using the Flash Programmer from the Command Line x
8.3.1. HPS Flash Programmer 8.3.2. HPS Flash Programmer Command Line Examples
9. Bare Metal Compilers x
9.1. Arm* Bare Metal Compilers 9.2. Linaro* GCC Compiler 9.3. Bare Metal Compilers Revision History
10. SD Card Boot Utility x
10.1. Usage Scenarios 10.2. Tool Options 10.3. SD Card Boot Utility Revision History
11. Linux* Device Tree Generator x
11.1. Linux* Device Tree Generator Revision History
12. Support and Feedback x
12.1. Support and Feedback Revision History
1. Introduction to the Intel® SoC FPGA Embedded Development Suite (SoC EDS)
2. Installing the Tools
3. Running the Tools
4. SoC EDS Licensing
5. Arm* Development Studio* for Intel® SoC FPGA Edition
6. Boot Tools User Guide
7. Hardware Library
8. Using the HPS Flash Programmer
9. Bare Metal Compilers
10. SD Card Boot Utility
11. Linux* Device Tree Generator
12. Support and Feedback

6.6. Boot Tools User Guide Revision History

Document Version Changes
2021.03.12 Updated the location to obtain the mkimage utility in the U-Boot Image Tool (mkimage) section
2020.08.07 Maintenance release.
2019.12.20 Supported with Intel® Quartus® Prime Standard Edition version 19.1 and Intel® Quartus® Prime Pro Edition version 19.3
  • Added support for Intel® Agilex™
  • Provided instruction on how to build the bootloader now that the BSP generator GUI is deprecated
  • Removed the following sections:
    • Using .tcl Scripts
    • Cyclone® V SoC and Arria® V SoC BSP Settings
    • U-Boot Build Flow
    • UEFI Build Flow
  • Moved the following sections to the Boot Tools User Guide Professional Edition:
    • Intel® Arria® 10 SoC BSP Settings
    • Intel® Arria® 10 SoC Main BSP Settings Group
    • Intel® Arria® 10 SoC Bootloader MPU Firewall BSP Settings Group
    • Intel® Arria® 10 SoC Bootloader L3 Firewall BSP Settings Group
    • Intel® Arria® 10 SoC Bootloader FPGA-to-SDRAM Firewall BSP Settings Group
  • Removed the following BSP Generator Command Line Interfaces that were deprecated:
    • bsp-update-settings
    • bsp-query-settings
    • bsp=generate-files
  • Provided instruction on how to configure the bootloader manually now that the BSP settings are deprecated
  • Provided details on how to build the bootloaders by pointing to "Building Bootloader" on RocketBoards.org
2019.05.16
  • Tool Usage section: Updated the mkpimage version to 19.1.
  • Building the Intel® Stratix® 10 SoC Bootloader section: In step 1, updated the path for the 19.1 release.
2018.09.24 Updated the path names, in the "Building the Intel® Stratix® 10 SoC Bootloader" section, to coincide with the 18.1 release.
2018.06.18
  • Updated chapter to include support for Intel® Stratix® 10 SoC
  • Replaced "Second Stage Bootloader" with "Bootloader".
  • Replaced "SSBL" with "FSBL"
  • Added the Intel® Stratix® 10 SoC Typical Boot Flow figure
  • Added the "Building the Intel® Stratix® 10 SoC Bootloader" section
2017.05.08
  • Intel FPGA rebranding
  • Rebranded paths and tools for the Standard and Professional versions
2016.11.7 Added an "UEFI Build Flow" section
2016.05.27 Added a link to the Intel® Arria® 10 SoC Secure Boot User Guide
2016.02.17
  • Updated the help definition for mkpimage in the "Tools Usage" and "Tool Options" sections
  • Updated the Intel® Arria® 10 SoC Main BSP Settings Group table
2015.08.06 Added Intel® Arria® 10 SoC support
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