High-Definition Multimedia Interface (HDMI) Intel® FPGA IP Release Notes

ID 683199
Date 4/09/2024
Public

1.14. Intel FPGA HDMI IP Core v17.1

Table 21.  v17.1 November 2017
Description Impact
Renamed the following as per Intel rebranding:
  • HDMI IP core to Intel FPGA HDMI IP core
  • Qsys to Platform Designer
The Support for deep color parameter is now turned on by default.
Added advanced support for Cyclone® 10 GX devices. The Cyclone® 10 GX devices are only available in the Quartus® Prime Pro Edition software.
Added support for up to 32 audio channels. These changes are optional. If you do not upgrade your IP core, it does not have these new features.
Added support for up to 1,536 kHz audio sample frequency.

In previous versions of the Intel FPGA HDMI design example for Arria® 10 devices, the IOPLL and transceiver PLL output may experience additional jitter. The additional jitter occurs if you source the reference clock from a cascaded PLL output, global clock, or core clock. To compensate for the jitter, the designs require additional constraints. This issue has been fixed in the Quartus® Prime software version 17.1.

If you are upgrading designs that have these additional constraints from the previous versions of the Quartus® Prime software to version 17.1, you must revise the constraints. Refer to the KDB page for more information.