AN 684: 100 Gbps CFP2 Design with Stratix V GT FPGAs

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ID 683219
Date 1/16/2014
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for 100 Gbps - CFP2 Interface
1. Design Guidelines for 100 Gbps - CFP2 Interface x
1.1. Stratix V GT Transceiver Channels 1.2. CFP2 Host Connector Assembly and Pinout 1.3. Stratix V GT to CFP2 Interface Layout Design 1.4. BGA Breakout Optimization 1.5. CFP2 Interface Optimization 1.6. Example Design Channel Performance 1.7. Document Revision History
1.3. Stratix V GT to CFP2 Interface Layout Design x
1.3.1. Board Stack Up Dimensions
1.6. Example Design Channel Performance x
1.6.1. Simulation Results for Stratix V GT to CFP2 Connector Layout Design
1. Design Guidelines for 100 Gbps - CFP2 Interface

1.4. BGA Breakout Optimization

BGA breakout optimization targets both the BGA pads and dog bone vias. A cutout is provided in the reference plane under the BGA pad and large oval via anti-pads are used for better BGA pad and via impedance matching.

Figure 8.  BGA Via Breakout Layout Optimization


Figure 9.  TDR of BGA Via Breakout HFSS simulation results show that the TDR deviation of the BGA escape is maintained within ±10% of the nominal 100Ω channel target impedance.


Level Two Title