Serial Lite IV Intel® Stratix™ 10 FPGA IP Design Example User Guide

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ID 683223
Date 11/01/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide 2. Quick Start Guide 3. Detailed Description for Serial Lite IV Design Example 4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for Serial Lite IV Design Example x
3.1. Features 3.2. Design Example Components 3.3. Simulation 3.4. Hardware Testing 3.5. Error Handling 3.6. Link Debugging Sequence 3.7. Serial Lite IV IP Toolkit
3.2. Design Example Components x
3.2.1. Traffic Generator 3.2.2. Traffic Checker 3.2.3. DCFIFO 3.2.4. System Console 3.2.5. Demo Management 3.2.6. Demo Control
3.3. Simulation x
3.3.1. Simulation Results for Basic Mode 3.3.2. Simulation Result for Full Mode
3.4. Hardware Testing x
3.4.1. Hardware Testing Result for Basic Transfer Mode 3.4.2. Hardware Testing Result for Full Transfer Mode 3.4.3. Traffic Statistic Results
3.7. Serial Lite IV IP Toolkit x
3.7.1. Setting Up and Running the Toolkit 3.7.2. Toolkit GUI Settings
1. About the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide
2. Quick Start Guide
3. Detailed Description for Serial Lite IV Design Example
4. Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide

5. Document Revision History for the Serial Lite IV Intel® Stratix® 10 FPGA IP Design Example User Guide

Document Version Intel® Quartus® Prime IP Version Changes
2021.11.01 21.3 1.3.1
  • Removed mentions of NCSim support throughout the document.
  • Added support for QuestaSim* simulator.
2021.04.01 21.1 1.3.1
  • Added transceiver reference clock information to Table: Design Example Components.
  • Updated Figure: Master and Slave Test Mode.
2020.06.22 20.2 1.2.0
  • Added the following sections:
    • PAM4 with RS-FEC Enabled in Basic Transfer Mode Simulation Result
    • NRZ without RS-FEC Enabled in Basic Transfer Mode Simulation Result
  • Added the following figures:
    • Example of System Console Printout for PAM4 with RS-FEC Enabled
    • Example of System Console Printout for NRZ with RS-FEC Enabled
    • Example of System Console Printout for PAM4 with RS-FEC Enabled
    • Example of System Console Printout for NRZ with RS-FEC Enabled
  • Added hardware testing description for:
    • loopback test mode
    • master and slave test mode
  • Added the Serial Lite IV Intel FPGA IP Release Notes link in the Related Documents table.
2020.04.13 20.1 1.2.0
  • Added slave test mode feature in the hardware design example.
  • Updated the Example Design Tab figure in the Design Example Parameters topic.
2019.09.30 19.3 1.1.0
  • Changed IP name to Serial Lite IV Intel FPGA IP.
  • Added support for NRZ and error handling features.
  • Updated directory structure for Serial Lite IV Intel FPGA IP design example.
  • Added a note to enable the Serial Lite IV Intel FPGA IP top-level signals to be captured in the simulation waveform when using ModelSim* - Intel® FPGA Edition simulator in Compiling and Simulating the Design topic.
  • Added note to clarify that ModelSim* - Intel® FPGA Edition not supported for in Serial Lite IV Intel FPGA IP in Compiling and Simulating the Design and Hardware and Software Requirementstopics.
  • Added samples of simulation log in the Simulation Result for Basic Streaming Mode and Simulation Result for Full Streaming Mode topics.
  • Updated value for lpm_width parameter in TX and RX DCFIFO Configuration table.
  • Updated rx_error signal width and its description in the Error Condition Behavior table.
  • Replaced wrfull and rdfull signals with tx_adaptation_full, rx_adaptation_full, and readfull signals in the Error Condition Behavior table.
  • Updated steps to launch the Serial Lite IV Intel FPGA IP toolkit in Setting Up and Running the Toolkit topic.
  • Added example of system console printouts in Hardware Testing topic.
  • Updated read_error_statistic command in Hardware Testing topic.
2019.07.01 19.2 1.0.0 Initial release.
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