Nios II Embedded Design Suite Release Notes

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ID 683228
Date 6/17/2015
Public
Document Table of Contents
Document Table of Contents x
1. Nios® II Embedded Design Suite Release Notes
1. Nios® II Embedded Design Suite Release Notes x
1.1. Product Revision History 1.2. Nios II EDS v15.0 Updates 1.3. Nios II EDS v14.1 Updates 1.4. Nios II EDS v14.0 Updates 1.5. Nios II EDS v13.1 Updates 1.6. Known Issues and Errata
1.3. Nios II EDS v14.1 Updates x
1.3.1. Nios II Gen2 Processor Core 1.3.2. New Embedded IPs for 14.1 1.3.3. 64-Bit Host Support Enhanced 1.3.4. Upgrades to the Eclipse Environment 1.3.5. Upgrades to the Nios II GNU Toolchain 1.3.6. Additional Support for Max10 1.3.7. Upgrades to the EPCQ IP Peripheral
1.4. Nios II EDS v14.0 Updates x
1.4.1. 64-Bit Host Support 1.4.2. Run-time Stack Checking 1.4.3. Long Jump Support 1.4.4. Floating Point Hardware 2 Support 1.4.5. Qsys Bridge Support 1.4.6. Nios II Gen2 Processor Support
1.4.6. Nios II Gen2 Processor Support x
1.4.6.1. The Nios II Gen2 Processor Core 1.4.6.2. HAL Support for the Nios II Gen2 Processor 1.4.6.3. Nios II Gen2 Processor and MAX 10 FPGA Support 1.4.6.4. What's New in v14.0a10: the Nios II Gen2 Processor and Arria 10 FPGA Support
1.4.6.3. Nios II Gen2 Processor and MAX 10 FPGA Support x
1.4.6.3.1. Nios II Gen2 Processor Cores and MAX 10 FPGA Support 1.4.6.3.2. Tool Support for the MAX 10 FPGA
1.5. Nios II EDS v13.1 Updates x
1.5.1. GCC Upgraded to 4.7.3 1.5.2. Enhanced Floating Point Custom Instruction Support 1.5.3. ECC Support 1.5.4. Universal Boot Copier
1. Nios® II Embedded Design Suite Release Notes

1.5.4. Universal Boot Copier

In v13.1, the Nios II boot copier is upgraded to support more types of flash devices.

The upgraded boot copier is called the universal boot copier.

The Nios II boot copier copies the application binaries from flash devices to volatile memory. The flash memory is laid out with the FPGA image at the lowest memory address, followed by the Nios II application binary images.

In previous product releases, the FPGA image size was fixed for each device family. However, for devices in the Cyclone V, Stratix V, and Arria V families, the image size varies depending on the following variables:

  • Flash type: Quad-output (EPCQ) or single-output (EPCS) Enhanced Programmable Configuration device
  • Flash device capacity: 128 or 256 Mbits
  • Compression
  • Serial peripheral interface (SPI) configuration: ×1 or ×4
  • Device layout: single or cascaded

It is difficult for the boot copier to identify the current combination so that it can use the appropriate image size, and any algorithm might fail to support future configurations.

To solve this problem, a header is added to the FPGA image to specify the image size. By using the image size from the header, the universal boot copier can work with any flash configuration in current or future devices.

The sof2flash utility is updated to support the universal boot copier.

This change does not impact to the ability of the FPGA control block to automatically program the FPGA image at power-on.

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