DMA Accelerator Functional Unit User Guide: Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA

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ID 683263
Date 3/06/2020
Public
Document Table of Contents
Document Table of Contents x
1. About this Document 2. DMA AFU Description 3. Register Map and Address Spaces 4. Software Programming Model 5. Running DMA AFU Example 6. Compiling the Accelerator Function (AF) 7. Simulating the AFU Example 8. DMA Accelerator Functional Unit User Guide Archives 9. Document Revision History for the DMA Accelerator Functional Unit User Guide A. Enabling Hugepages
1. About this Document x
1.1. Intended Audience 1.2. Conventions 1.3. Acronyms 1.4. Acceleration Glossary
2. DMA AFU Description x
2.1. Introduction 2.2. The DMA AFU Software Package 2.3. The DMA AFU Hardware Components
2.3. The DMA AFU Hardware Components x
2.3.1. DMA Test System 2.3.2. DMA BBB
3. Register Map and Address Spaces x
3.1. DMA AFU Register Map
3.1. DMA AFU Register Map x
3.1.1. DMA AFU Address Space
4. Software Programming Model x
4.1. Software APIs
4.1. Software APIs x
4.1.1. fpgaDmaOpen() 4.1.2. fpgaDmaTransferSync() 4.1.3. fpgaDmaClose()
5. Running DMA AFU Example x
5.1. Optimization for Improved DMA Performance
1. About this Document
2. DMA AFU Description
3. Register Map and Address Spaces
4. Software Programming Model
5. Running DMA AFU Example
6. Compiling the Accelerator Function (AF)
7. Simulating the AFU Example
8. DMA Accelerator Functional Unit User Guide Archives
9. Document Revision History for the DMA Accelerator Functional Unit User Guide
A. Enabling Hugepages

4.1.2. fpgaDmaTransferSync()

fpgaDmaTransferSync() accepts a handle to an opened DMA and performs a transfer of data from the source address to the destination address. This function is a blocking call and returns when the DMA transfer completes.

Prototype fpga_result fpgaDmaTransferSync(fpga_dma_handle dma, uint64_t dst, uint64_t src, size_t count, fpga_dma_transfer_t type)
Arguments dma

dmaInput specifying DMA handle obtained from fpgaDmaOpen().

dst

Input specifying the destination byte address of the transfer. To maximize performance, make dst a multiple of 64 bytes.

src

Input specifying the source byte address of the transfer. To maximize performance, make src a multiple of 64 bytes.

count

Input specifying the length of the transfer in bytes. To maximize performance, make count a multiple of 64 bytes.

type

Input specifying the type of transfer. type has the following valid values: HOST_TO_FPGA_MM, FPGA_TO_HOST_MM, or FPGA_TO_FPGA_MM.

Returns FPGA_OK on success; otherwise error return code.
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