Intel® Stratix® 10 SX SoC Development Kit User Guide

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ID 683303
Date 6/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Kit Setup 4. Development Kit Components 5. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Kit Description 1.2. Recommended Operating Conditions 1.3. Handling the Development Kit
2. Getting Started x
2.1. Installing Quartus Prime Software 2.2. Installing the Intel® FPGA Download Cable 2.3. Installing the Intel SoC Embedded Development Suite (EDS) 2.4. Installing the Intel® Stratix® 10 SX SoC Development Kit Package
3. Development Kit Setup x
3.1. Inspect the Development Kit 3.2. Default Setup of the Development Kit 3.3. Intel® MAX® 10 System Controller Updates
4. Development Kit Components x
4.1. Development Kit Feature Summary 4.2. Board Components 4.3. Intel® Stratix® 10 SoC Device Overview 4.4. Intel® MAX® 10 System Controller Overview 4.5. FPGA Configuration 4.6. General User Input/Output 4.7. Connectors and Interfaces 4.8. Daughter Cards 4.9. System Memory 4.10. System Power
4.7. Connectors and Interfaces x
4.7.1. PCIe* Slot 4.7.2. ZQSFP+ 4.7.3. SFP+ 4.7.4. HDMI 4.7.5. SDI Port 4.7.6. MXP 4.7.7. Intel® FPGA Download Cable Direct Port (Debug Port) 4.7.8. FMC+ A/B Slot 4.7.9. FMC+ A/B LVDS Interfaces (LPC Pins) 4.7.10. LMK05028 Jitter Attenuator 4.7.11. FPGA-IOMAX10 Interface
4.8. Daughter Cards x
4.8.1. HPS IO-48 OOBE Daughter Card 4.8.2. HPS IO-48 NAND Flash Daughter Card 4.8.3. HPS Boot Flash Card
4.8.3. HPS Boot Flash Card x
4.8.3.1. Boot QSPI Flash Daughter Card 4.8.3.2. Boot MicroSD Daughter Card 4.8.3.3. Boot eMMC Daughter Card
4.9. System Memory x
4.9.1. FPGA Memory (DDR4 SO-DIMM) 4.9.2. HPS Memory (External 4 GB HILO x72 DDR4 ) 4.9.3. HPS I2C Interface
4.10. System Power x
4.10.1. Power Supply Options 4.10.2. Power Sequence 4.10.3. Power Distribution Network
5. Board Test System x
5.1. Preparing the Board 5.2. Running the BTS 5.3. Using the BTS
5.3. Using the BTS x
5.3.1. The Configure Menu 5.3.2. The GPIO Tab 5.3.3. The QSFP/SFP Tab 5.3.4. The PCIE Tab 5.3.5. The MXP Tab 5.3.6. The FMCA Tab 5.3.7. The FMCB Tab 5.3.8. The DDR4 Tab 5.3.9. Power Monitor 5.3.10. The Clock Control
A. Additional Information x
A.1. Modify the Intel® Stratix® 10 SX SoC Development Kit to use a battery for the BBRAM A.2. Modify the Intel® Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project A.3. Safety and Regulatory Information A.4. Compliance Information
A.3. Safety and Regulatory Information x
A.3.1. Safety Warnings A.3.2. Safety Cautions
A.4. Compliance Information x
A.4.1. Compliance and Conformity Statements
B. Revision History x
B.1. Revision History
1. Overview
2. Getting Started
3. Development Kit Setup
4. Development Kit Components
5. Board Test System
A. Additional Information
B. Revision History

A.2. Modify the Intel® Stratix® 10 SX SoC Development Kit HPS DDR4 memory width and ECC configuration using the Golden Hardware Reference Design project

The supported HPS DDR4 configurations are:
  • 72 bits : 64 bit data + 8 bit ECC
  • 64 bits : 64 bit data
  • 40 bits : 32 bit data + 8 bit ECC
  • 32 bits : 32 bit data
  • 24 bits : 16 bit data + 8 bit ECC
  • 16 bits : 16 bit data

The Golden Hardware Reference Design (GHRD) project has an HPS DDR4 interface configuration with a width of 72 bits.

Flow to modify the HPS DDR4 memory width and ECC Configuration

  1. Open the qsys_top.qsys file. Select the emif_hps component and open the Parameter Editor. Change the Memory tab > DQ width as required. If ECC isn’t required, unselect the Controller tab parameters Enable Error Detection and Correction Logic with ECC and Enable Auto Error Correction to External Memory. Generate the qsys component.
  2. Open the top level RTL file ghrd_s10_top.v. At the top, change the input wire bus width declarations for emif_hps_mem_mem_dbi_n, emif_hps_mem_mem_dq, emif_hps_mem_mem_dqs and emif_hps_mem_mem_dqs_n for your required DDR4 configuration.
  3. In the Quartus Assignment Editor or in the project .qsf file, make these changes:
    • For the required DDR4 interface width, disable all the location assignments of the unused mem_dbi_n, mem_dqs, mem_dqs_n and mem_dq signals.
    • For narrower width interfaces with ECC, in order to meet the pinout rules in the Intel® Stratix® 10 SoC Design Guidelines and the Intel® Stratix® 10 EMIF IP User Guide's HPS DQS group placements, the DQS group used for the ECC bits needs to move so it is placed in lane 3 of I/O bank 2M.
    • For a DDR4 interface width of 16 bit + ECC, copy the pin locations for emif_hps_mem_mem_dbi_n [8], emif_hps_mem_mem_dqs[8], emif_hps_mem_mem_dqs_n[8], emif_hps_mem_mem_dq[71:64], to emif_hps_mem_mem_dbi_n[2], emif_hps_mem_mem_dqs[2], emif_hps_mem_mem_dqs_n[2], emif_hps_mem_mem_dq[23:16] respectively.
    • For a DDR4 interface width of 32 bit + ECC, copy the pin locations for emif_hps_mem_mem_dbi_n [8], emif_hps_mem_mem_dqs[8], emif_hps_mem_mem_dqs_n[8], emif_hps_mem_mem_dq[71:64], to emif_hps_mem_mem_dbi_n[4], emif_hps_mem_mem_dqs[4], emif_hps_mem_mem_dqs_n[4], emif_hps_mem_mem_dq[39:32] respectively.
Note: Note the alert# pin is placed in DQS group 0 which is always in the GHRD project regardless of the HPS DDR4 interface width, so no changes are needed.
Note: Further details for some configurations are shown in Enabling ECC for HPS SDRAM Article on RocketBoards website.
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