Video and Vision Processing Suite Intel® FPGA IP User Guide

ID 683329
Date 2/15/2022
Public

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11.4. Clocked Video Converter to Full Raster IP Registers

The IP allows runtime configuration of parameters using the Avalon memory-mapped processor register interface. Unless stated, all registers are 32-bit wide.
Table 110.  Processor Register Description
Common registers
Register Offset Access Description
Reg_HV_Pos 0x140 RW Specify the H and V position of the rising edge of the vsync pulse occurs.
Reg_Total_HV 0x144 RO Shows the IP's total width and total height, including active pixels and blanking.
Clocked video input specific registers
Reg_CVI_Legacy_0 0x148 RW Drives legacy clocked video input conduit output signals and returns the current values.
Reg_CVI_Legacy 1 0x14C RO Drives legacy clocked video input conduit output signals and returns the current values.
Clocked video output specific registers
Reg_CVO_Legacy_0 0x150 RO The current value of the clocked video output conduit sideband signals vid_sof.
Table 111.  Reg_HV_Pos
Name Bits Attribute Description
H Position 15:0 RW Specify the video pixel on which the rising edge of the vsync pulse occurs
V Position 31:16 RW Specify the video line on which the rising edge of the vsync pulse occurs is the reset bit
Table 112.  Reg_Total_HV
Name Bits Attribute Description
Total Pixels 15:0 RO Shows the IP's width of the video line, including active pixels and horizontal blanking.
Total Lines 31:16 RO Shows the IP's height of the video, including active lines and vertical blanking.
Table 113.   Reg_CVI_Legacy_0
Name Bits Attribute Description
CVI SOF 0 RW Drives legacy clocked video input conduit signal sof.
CVI SOF Locked 1 RW Drives legacy clocked video input conduit signal sof_locked.
CVI Overflow 2 RW Drives legacy clocked video input conduit signal overflow.
CVI Clipping 3 RW Drives legacy clocked video input conduit signal clipping.
CVI Padding 4 RW Drives legacy clocked video input conduit signal padding.
CVI refclk_div 5 RW Drives legacy clocked video input conduit signal refclk_div.
Reserved 7:6 - Reserved.
CVI video locked 8 RO The current value of the clocked video input legacy signal vid_locked.
Reserved 15:9 - Reserved.
CVI color encoding 23:16 RO The current value of the clocked video input legacy signal vid_color_encoding.
CVI bit width 31:24 RO The current value of the clocked video input legacy signal vid_bit_width.
Table 114.  Reg_clocked video input_Legacy_1
Name Bits Attribute Description
CVI vid std STD_WIDTH-1:0 RO The current value of the clocked video input legacy signal vid_std.
CVI HDMI duplication 19:16 RO The current value of the clocked video input signal vid_hdmi_duplication.
Reserved 23:20 - Reserved.
CVI HD not SD 24 RO The current value of the clocked video input signal vid_hd_sdn.
Reserved 31:25 - Reserved.
Table 115.  Reg_CVO_Legacy_0
Name Bits Attribute Description
CVO SOF 0 RO The value of the input legacy clocked video output conduit signal vid_sof.
CVO SOF Locked 1 RO The value of the input legacy clocked video output conduit signal vid_sof_locked.
CVO Underflow 2 RO The value of the input legacy clocked video output conduit signal underflow.
CVO vco clock divide 3 RO The value of the input legacy clocked video output conduit signal vid_vcoclk_div.
CVO mode change 4 RO The value of the input legacy clocked video output conduit signal vid_mode_change.
Reserved 15:5 - Reserved.
CVO video standard STD_WIDTH+15:16 RO The value of the input legacy clocked video output conduit signal vid_std.