Arria® 10 Device Overview

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ID 683332
Date 2/14/2022
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Document Table of Contents
Document Table of Contents x
Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Overview x
Key Advantages of Intel® Arria® 10 Devices Summary of Intel® Arria® 10 Features Intel® Arria® 10 Device Variants and Packages I/O Vertical Migration for Intel® Arria® 10 Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1, Gen2, and Gen3 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers SoC with Hard Processor System Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Arria® 10 Device Overview
Intel® Arria® 10 Device Variants and Packages x
Intel® Arria® 10 GX Intel® Arria® 10 GT Intel® Arria® 10 SX
Intel® Arria® 10 GX x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 GT x
Available Options Maximum Resources Package Plan
Intel® Arria® 10 SX x
Available Options Maximum Resources Package Plan
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Intel® Arria® 10 Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Intel® Arria® 10 Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
SoC with Hard Processor System x
Key Advantages of 20-nm HPS Features of the HPS FPGA Configuration and HPS Booting Hardware and Software Development
Features of the HPS x
System Peripherals and Debug Access Port HPS–FPGA AXI Bridges HPS SDRAM Controller Subsystem
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Intel® Arria® 10 Device Overview

Package Plan

Table 13.  Package Plan for Intel® Arria® 10 SX Devices (U19, F27, F29, and F34)Refer to I/O and High Speed I/O in Intel® Arria® 10 Devices chapter for the number of 3 V I/O, LVDS I/O, and LVDS channels in each device package.

Product Line

U19

(19 mm × 19 mm, 484-pin UBGA)

F27

(27 mm × 27 mm, 672-pin FBGA)

F29

(29 mm × 29 mm, 780-pin FBGA)

F34

(35 mm × 35 mm, 1152-pin FBGA)

3 V I/O LVDS I/O XCVR 3 V I/O LVDS I/O XCVR 3 V I/O LVDS I/O XCVR 3 V I/O LVDS I/O XCVR
SX 160 48 144 6 48 192 12 48 240 12 — — —
SX 220 48 144 6 48 192 12 48 240 12 — — —
SX 270 — — — 48 192 12 48 312 12 48 336 24
SX 320 — — — 48 192 12 48 312 12 48 336 24
SX 480 — — — — — — 48 312 12 48 444 24
SX 570 — — — — — — — — — 48 444 24
SX 660 — — — — — — — — — 48 444 24
Table 14.  Package Plan for Intel® Arria® 10 SX Devices (F35, KF40, and NF40)Refer to I/O and High Speed I/O in Intel® Arria® 10 Devices chapter for the number of 3 V I/O, LVDS I/O, and LVDS channels in each device package.

Product Line

F35

(35 mm × 35 mm, 1152-pin FBGA)

KF40

(40 mm × 40 mm, 1517-pin FBGA)

NF40

(40 mm × 40 mm, 1517-pin FBGA)

3 V I/O LVDS I/O XCVR 3 V I/O LVDS I/O XCVR 3 V I/O LVDS I/O XCVR
SX 270 48 336 24 — — — — — —
SX 320 48 336 24 — — — — — —
SX 480 48 348 36 — — — — — —
SX 570 48 348 36 96 600 36 48 540 48
SX 660 48 348 36 96 600 36 48 540 48
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