E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683357
Date 10/02/2023
Public
Document Table of Contents
Document Table of Contents x
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide 2. JESD204C Intel® FPGA IP Design Example Quick Start Guide 3. Detailed Description for the JESD204C Design Example 4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 5. Document Revision History for the E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide x
2.1. Design Example Block Diagram 2.2. Hardware and Software Requirements 2.3. Generating the Design 2.4. Compiling and Simulating the Design 2.5. Compiling and Testing the Design
2.3. Generating the Design x
2.3.1. Design Example Parameters 2.3.2. Directory Structure
3. Detailed Description for the JESD204C Design Example x
3.1. System Components 3.2. JESD204C Design Example Clock and Reset 3.3. JESD204C Design Example Signals 3.4. JESD204C Design Example Control Registers 3.5. Hardware Test for System Console Control Design Example
3.1. System Components x
3.1.1. JTAG to Avalon® Master Bridge 3.1.2. Parallel I/O (PIO) Core 3.1.3. SPI Master 3.1.4. SYSREF Generator 3.1.5. Pattern Generator and Checker
3.5. Hardware Test for System Console Control Design Example x
3.5.1. Board Connectivity
1. About the JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide
2. JESD204C Intel® FPGA IP Design Example Quick Start Guide
3. Detailed Description for the JESD204C Design Example
4. E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide Archives
5. Document Revision History for the E-Tile JESD204C Intel® Stratix® 10 FPGA IP Design Example User Guide

2.3.1. Design Example Parameters

The JESD204C Intel® FPGA IP parameter editor includes the Example Design tab for you to specify certain parameters before generating the design example.
Table 6.  Parameters in the Example Design Tab
Parameter Options Description
Select Design
  • System Console Control
  • None
 Select the system console control to access the design example data path through the system console.
Simulation On, Off Turn on for the IP to generate the necessary files for simulating the design example.
Synthesis On, Off Turn on for the IP to generate the necessary files for Intel® Quartus® Prime compilation and hardware demonstration.
HDL format (for simulation) Verilog only Select the HDL format of the RTL files for simulation.
HDL format (for synthesis) Verilog only Select the HDL format of the RTL files for synthesis.
Generate 3-wire SPI module On, Off

Turn on to enable 3-wire SPI interface instead of 4-wire.
Sysref mode
  • One-shot
  • Periodic
  • Gapped periodic

Select whether you want the SYSREF alignment to be a one-shot pulse mode, periodic, or gapped periodic, based on your design requirements and timing flexibility.

  • One-shot: Select this option to enable SYSREF to be a one-shot pulse mode. The sysref_ctrl[17] register bit's value is 0. After the JESD204C IP reset deasserts, change the sysref_ctrl[17] register's value from 0 to 1, then to 0, for a one-shot SYSREF pulse.
  • Periodic: SYSREF in periodic mode has 50:50 duty cycle. SYSREF period is E*SYSREF_MULP.
  • Gapped periodic: SYSREF has programmable duty cycle of granularity of 1 link clock cycle. SYSREF period is E*SYSREF_MULP. For out-of-range duty cycle setting, the SYSREF generation block should automatically infer 50:50 duty cycle.
Refer to SYSREF Generator for more information about the SYSREF period.
Select board
  • None
  • S10 TX SI Devkit ( Intel® Stratix® 10 TX Signal Integrity Development Kit)
Select the board for the design example.
  • None: This option excludes hardware aspects for the design example. All the pin assignments are set to virtual pins.
  • Intel® Stratix® 10 TX Signal Integrity Development Kit: This option automatically selects the project’s target device to match the device on this development kit. You may change the target device with the Change Target Device parameter below if your board revision has a different grade of the default targeted device. All the pin assignments are set according to the development kit.
Test pattern
  • PRBS-7
  • PRBS-9
  • PRBS-15
  • PRBS-23
  • Ramp

Select the patten generator and checker test pattern to either ramp or one of the PRBS pattern options.

The PRBS options are some of the commonly used degree of polynomials.
Note: To switch the PRBS polynomial options, change this parameter, and generate and recompile the design example.

If you select PRBS pattern, the pattern checker expects the scrambling seed to be self-synchronized when the deskew alignment is achieved by the JESD204C RX IP.

If you select ramp pattern, the first valid data sample for each converter (M) is loaded as the initial value. Subsequent data sample values must increase by 1 in each clock cycle up to the maximum and then roll over to 0. For example, when S=1, N=16 and WIDTH_MULP = 2, the data width per converter is S*WIDTH_MULP*N=32. The maximum data sample value is 0xFFFF.

The ramp pattern checker verifies that identical patterns are received across all converters.

Enable internal serial loopback (Simulation) On, Off Turn on to enable internal serial loopback. If you turn on this option, the RX path takes the serial input from the TX path internally in the FPGA.
Enable command channel pattern (Simulation) On, Off Turn on to enable command channel pattern.
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