AN 919: Improving Quality of Results with Design Assistant

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ID 683369
Date 4/26/2024
Public
Document Table of Contents
Document Table of Contents x
Improving Quality of Results with Design Assistant Document Revision History for AN 919: Improving Quality of Results with Design Assistant Appendix A: Running Design Assistant Appendix B: Design Assistant Rules
Improving Quality of Results with Design Assistant x
About Design Assistant About the Design Assistant Design Example Fixing SDC and CDC Rules in the Design Assistant Design Example Fixing Other Faults in the Design Assistant Design Example
Appendix A: Running Design Assistant x
Running Design Assistant
Appendix B: Design Assistant Rules x
Timing Closure Rules Clock Domain Crossing and Reset Domain Crossing Rules Intrinsic Margin Rules Combinatorial Logic Levels Reducing High Fan-out Nets Hyper-Retimer Restrictions Initial Power-Up Conditions Rules Reset Release Intel FPGA IP
Reducing High Fan-out Nets x
Duplication Rules Tension and Span Rules
Initial Power-Up Conditions Rules x
Removing Initial Power-Up Conditions
Improving Quality of Results with Design Assistant
Document Revision History for AN 919: Improving Quality of Results with Design Assistant
Appendix A: Running Design Assistant
Appendix B: Design Assistant Rules

Combinatorial Logic Levels

The number of combinatorial logic between registers can increase the path delay and limit fMAX. To reach higher clock speeds, reduce the levels of combinatorial logic.

To reduce the levels of combinatorial logic:

  • Add additional pipeline stages. With additional pipelining resources, the retimer can reduce the logic levels by balancing the register chain.
  • Look for design optimizations that can reduce logic levels. For example, include precomputing values, or computing more in parallel.

Rule TMC-20010 detects paths levels above a given threshold on the worst timing paths.

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