LDPC IP Core User Guide

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ID 683381
Date 4/04/2022
Public
Document Table of Contents
Document Table of Contents x
Product Discontinuance Notification 2. LDPC IP EOL 2. About the LDPC IP Core 3. Getting Started with the LDPC IP Core 4. LDPC IP Core Specifications 5. Document Revision History A. LDPC IP Core Document Archive
2. About the LDPC IP Core x
2.1. LDPC IP Core Features 2.2. LDPC IP Device Family Support 2.3. LDPC IP Core Release Information 2.4. DSP Intel® FPGA IP Verification 2.5. LDPC IP Core Performance
3. Getting Started with the LDPC IP Core x
3.1. Installing and Licensing Intel® FPGA IP Cores 3.2. IP Catalog and Parameter Editor 3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) 3.4. Simulating Intel® FPGA IP Cores
3.1. Installing and Licensing Intel® FPGA IP Cores x
3.1.1. Intel® FPGA IP Evaluation Mode 3.1.2. LDPC IP Core Intel® FPGA IP Evaluation Mode Timeout Behavior
3.3. Specifying the IP Core Parameters and Options ( Intel® Quartus® Prime Pro Edition) x
3.3.1. IP Core Generation Output ( Intel® Quartus® Prime Pro Edition)
4. LDPC IP Core Specifications x
4.1. LDPC IP Core Interfaces 4.2. LDPC IP Core Parameters
4.1. LDPC IP Core Interfaces x
4.1.1. Avalon Streaming Interfaces in DSP Intel FPGA IP 4.1.2. Clock and Reset Interfaces 4.1.3. LDPC IP Core Signals
4.1.3. LDPC IP Core Signals x
4.1.3.1. LDPC IP Core Backpressure
Product Discontinuance Notification
2. LDPC IP EOL
2. About the LDPC IP Core
3. Getting Started with the LDPC IP Core
4. LDPC IP Core Specifications
5. Document Revision History
A. LDPC IP Core Document Archive

2.1. LDPC IP Core Features

The LDPC IP Core targets these standards:

  • DOCSIS 3.1
    • Decoder only
    • On-the fly switching between code
  • WiMedia 1.5
    • Encoder and decoder
    • Optional on-the fly switching between code
    • Supports short and long frame
  • DVB-S2
    • Encoder only
  • NASA GSFC-STD-9100
    • Encoder and decoder
    • Optional low resource architecture
    • MSA or layered MSA decoding

All decoders have:

  • MATLAB models
  • Double-buffered architecture to reduce latency and boost throughput
  • Early stopping criterion
  • Parameters for:
    • Input parallelism
    • Decoding parallelism
    • LLR width
    • Attenuation factor
Level Two Title