AN 807: Configuring the Intel® Arria® 10 GX FPGA Development Kit for the Intel® FPGA SDK for OpenCL™

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ID 683446
Date 2/14/2020
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Configuring the Intel® Arria® 10 GX FPGA Development Kit for the Intel® FPGA SDK for OpenCL™
Configuring the Intel® Arria® 10 GX FPGA Development Kit for the Intel® FPGA SDK for OpenCL™ x
Configuring and Installing the Intel® Arria® 10 GX FPGA Development Kit board Initializing the Intel® Arria® 10 GX FPGA Development Kit for use with OpenCL* Installing the OpenCL Runtime Driver Programming the Flash Memory on the Intel® Arria® 10 GX FPGA Development Kit Troubleshooting Document Revision History of Configuring the Intel® Arria® 10 GX FPGA Development Kit for the Intel® FPGA SDK for OpenCL™
Configuring the Intel® Arria® 10 GX FPGA Development Kit for the Intel® FPGA SDK for OpenCL™

Initializing the Intel® Arria® 10 GX FPGA Development Kit for use with OpenCL*

Before you can use the Intel® Arria® 10 GX FPGA Development Kit with OpenCL* , you must initialize the board with an OpenCL* image. Without this image, the board host operating system does not recognize the PCIe card and the Intel® FPGA SDK for OpenCL™ Offline Compiler cannot find the device.

Before you initialize the Intel® Arria® 10 GX FPGA Development Kit for use with the Intel® FPGA SDK for OpenCL™ , install the following software on the system where you installed the PCIe card:

To initialize the Intel® Arria® 10 GX FPGA Development Kit for use with OpenCL* :

  1. Lower the JTAG clock speed to 6 MHz using the following command: 
    jtagconfig --setparam 1 JtagClock 6M

    If you receive " No JTAG hardware available " error message, refer to The jtagconfig command fails when initializing the Intel Arria 10 GX FPGA Development Kit for use with OpenCL for solution.

    You can confirm the clock speed with the following command:

    jtagconfig --getparam 1 JtagClock
  2. Uncompress the following file to a temporary location: 
    INTELFPGAOCLSDKROOT/board/a10_ref/bringup/a10_ref_initialization.tgz
    Where INTELFPGAOCLSDKROOT in the installation path for the Intel® FPGA SDK for OpenCL™ .

    Ensure that you have the following files in your temporary location. You need these files to complete the steps that follow.

    • max5_150.pof
    • top.sof
    • boardtest.aocx
  3. Update the MAX V CPLD system controller with the max5_150.pof file as follows:
    1. Ensure that cable number 1 is the cable connected to the Intel® Arria® 10 GX FPGA Development Kit with the following command: 
      quartus_pgm -l

      The command output should resemble the following example output:

      Info: Command: quartus_pgm -l
1) USB-BlasterII [2-1.3]                      
Info: Quartus Prime Programmer was successful. 0 errors, 0 warnings
    1. Run the jtagconfig command as follows to ensure that your Intel® FPGA Download Cable driver is ready: 
      bash-4.1$ jtagconfig

1) USB-BlasterII [2-1.1]                      
  02E060DD   10AT115N(2E2|3E2|4E2)/..
  020A40DD   5M2210Z/EPM2210
    2. Run the following command to update the MAX V CPLD system controller: 
      quartus_pgm -c 1 -m JTAG -o "p;max5_150.pof@2"
  4. Program the FPGA on your Intel® Arria® 10 GX FPGA Development Kit with the top.sof file by running the following command: 
    quartus_pgm -c 1 -m JTAG -o "p;top.sof"

    If you see an unexpected reboot of your system, refer to Unexpected reboot during programming the FPGA for solution.

  5. Perform a soft reboot (sometimes called a warm reboot) of your host system. On Linux systems, use the /sbin/reboot command to perform a soft reboot.

    After you program the FPGA and perform a soft reboot, the host system should recognize the Intel® Arria® 10 GX FPGA Development Kit PCIe card. Your system must recognize the card before you load the Intel® FPGA SDK for OpenCL™ driver.

After preparing your Intel® Arria® 10 GX FPGA Development Kit for the compiler, install the OpenCL* runtime driver, program the flash memory, and run a diagnostic test to confirm that board initialization was successful.
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