AN 776: UHD HDMI 2.0 Video Format Conversion Design Example

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ID 683465
Date 4/15/2021
Public
Document Table of Contents
Document Table of Contents x
1. About the UHD HDMI 2.0 Video Format Conversion Design Example 2. UHD HDMI 2.0 Video Format Conversion Design Example Getting Started 3. UHD HDMI 2.0 Video Format Conversion Design Example Functional Description 4. Considering Design Security 5. UHD HDMI 2.0 Video Format Conversion Design Example Document Revision History A. HDMI RX Interface Register Map B. HDMI TX Interface Register Map
1. About the UHD HDMI 2.0 Video Format Conversion Design Example x
1.1. UHD HDMI 2.0 Video Format Conversion Design Example Features
2. UHD HDMI 2.0 Video Format Conversion Design Example Getting Started x
2.1. Hardware and Software Requirements for the UHD HDMI 2.0 Video Format Conversion Design Example 2.2. Downloading and Installing the UHD HDMI 2.0 Video Format Conversion Design Example 2.3. Setting up the Intel® Arria® 10 FPGA development board 2.4. Compiling the UHD HDMI 2.0 Video Format Conversion Design Example 2.5. Compiling the UHD HDMI 2.0 Video Format Conversion Design Example with the Nios II Software Tools for Eclipse 2.6. Running the UHD HDMI 2.0 Video Format Conversion Design Example on the Hardware
2.2. Downloading and Installing the UHD HDMI 2.0 Video Format Conversion Design Example x
2.2.1. Installation Files for the UHD HDMI 2.0 Video Format Conversion Design Example
2.3. Setting up the Intel® Arria® 10 FPGA development board x
2.3.1. Board Status Lights, DIP Switches, and Pushbuttons
3. UHD HDMI 2.0 Video Format Conversion Design Example Functional Description x
3.1. Software Description
1. About the UHD HDMI 2.0 Video Format Conversion Design Example
2. UHD HDMI 2.0 Video Format Conversion Design Example Getting Started
3. UHD HDMI 2.0 Video Format Conversion Design Example Functional Description
4. Considering Design Security
5. UHD HDMI 2.0 Video Format Conversion Design Example Document Revision History
A. HDMI RX Interface Register Map
B. HDMI TX Interface Register Map

2.6. Running the UHD HDMI 2.0 Video Format Conversion Design Example on the Hardware

Download the compiled .sof for the design to the Intel Arria 10 GX FPGA Development Kit and run the design.
  1. In the Intel® Quartus® Prime software, click Tools > Programmer.
  2. In the Programmer window, click Auto Detect to scan the JTAG chain and discover the connected devices.
    If a pop-up window appears with the message do you want to update the programmer’s device list, click Yes.
  3. In the device list, select the row labelled 10AX115S2F45 and click Change File… then:
    1. To use the precompiled .sof included with the design, select the .sof in the master_image directory.
    2. To use your compiled .sof, select the .sof in the output_files directory.
  4. Turn on Program/Configure in the 10AX115S2F45 row.
  5. Click Start.
    When the programmer completes, the design runs automatically.
  6. If you set user DIP switch 1 is to the ON position, open a Nios II terminal to receive the output text messages from the design, otherwise the design locks. If user DIP Switch 1 is set to off, do not open the Nios II terminal.
    1. Open a terminal window and type nios2-terminal and press enter.
    When the design is running, output appears on the display, even if no source is connected at the input. The output is a black screen with the Intel icon in the top right-hand corner of the screen. If you build the software using the Nios II Software Build Tools for Eclipse, you can edit, compile, and download the software programming file at any point after you program the board.
  7. In the Nios II – Eclipse window, run the vip_control.elf programming file created by the Eclipse build .
    If a Nios II terminal window is already open, close it before trying to download new software.
    1. Right click on the vip_control folder in the Project Explorer tab of the Nios II – Eclipse window.
    2. Select Run As > Nios II Hardware.
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