Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs Version 1.2.1 Release Notes

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ID 683480
Date 3/06/2020
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Document Table of Contents
Document Table of Contents x
Notice About this Document Minimum Requirements Intel® Acceleration Stack Reference Table Intel® Acceleration Stack v1.2.1 Enhancements Known Issues for the Intel Acceleration Stack v1.2.1 Known Issues for the Intel Acceleration Stack v1.2.1 AFU Design Examples Resolved Issues from v1.2 to v1.2.1 Intel Acceleration Stack Release Notes Archives Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v1.2.1 Release Notes Revision History
About this Document x
Acronym List
Notice
About this Document
Minimum Requirements
Intel® Acceleration Stack Reference Table
Intel® Acceleration Stack v1.2.1 Enhancements
Known Issues for the Intel Acceleration Stack v1.2.1
Known Issues for the Intel Acceleration Stack v1.2.1 AFU Design Examples
Resolved Issues from v1.2 to v1.2.1
Intel Acceleration Stack Release Notes Archives
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs v1.2.1 Release Notes Revision History

Minimum Requirements

The minimum requirements for the Intel® Programmable Acceleration Card with Intel® Arria® 10 GX FPGA must include:
  • Intel® Xeon® Scalable processor
  • A PCI Express* x16 Slot
  • 48 GB of free memory is a requirement only if you are compiling a hardware design
  • Operating System:
    • Red Hat* Enterprise Linux* (RHEL) version 7.6
    • Ubuntu* version 18.04
  • Board management controller (BMC) Firmware and Bootloader Version: 26895
  • PACSign tool requires Python 3.0
  • OPAE tools require Python 2.7
  • OpenCL* RTE version 19.4.0.64
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