Cyclone® 10 GX Device Overview

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ID 683485
Date 4/01/2019
Public
Document Table of Contents
Document Table of Contents x
Intel® Cyclone® 10 GX Device Overview
Intel® Cyclone® 10 GX Device Overview x
Key Advantages of Intel® Cyclone® 10 GX Devices Summary of Intel® Cyclone® 10 GX Features Intel® Cyclone® 10 GX Available Options Intel® Cyclone® 10 GX Maximum Resources Intel® Cyclone® 10 GX Package Plan I/O Vertical Migration for Intel® Cyclone® 10 GX Devices Adaptive Logic Module Variable-Precision DSP Block Embedded Memory Blocks Clock Networks and PLL Clock Sources FPGA General Purpose I/O External Memory Interface PCIe Gen1 and Gen2 Hard IP Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet Low Power Serial Transceivers Dynamic and Partial Reconfiguration Enhanced Configuration and Configuration via Protocol SEU Error Detection and Correction Power Management Incremental Compilation Document Revision History for Intel® Cyclone® 10 GX Device Overview
Embedded Memory Blocks x
Types of Embedded Memory Embedded Memory Capacity in Intel® Cyclone® 10 GX Devices Embedded Memory Configurations for Single-port Mode
Clock Networks and PLL Clock Sources x
Clock Networks Fractional Synthesis and I/O PLLs
Fractional Synthesis and I/O PLLs x
Fractional Synthesis PLLs I/O PLLs
External Memory Interface x
Memory Standards Supported by Intel® Cyclone® 10 GX Devices
Enhanced PCS Hard IP for Interlaken and 10 Gbps Ethernet x
Interlaken Support 10 Gbps Ethernet Support
Low Power Serial Transceivers x
Transceiver Channels PMA Features PCS Features
PCS Features x
PCS Protocol Support
Dynamic and Partial Reconfiguration x
Dynamic Reconfiguration Partial Reconfiguration
Intel® Cyclone® 10 GX Device Overview

PMA Features

Intel® Cyclone® 10 GX transceivers provide exceptional signal integrity at data rates up to 12.5 Gbps. Clocking options include ultra-low jitter ATX PLLs (LC tank based), clock multiplier unit (CMU) PLLs, and fractional PLLs.

Each transceiver channel contains a channel PLL that can be used as the CMU PLL or clock data recovery (CDR) PLL. In CDR mode, the channel PLL recovers the receiver clock and data in the transceiver channel.

Table 12.  PMA Features of the Transceivers in Intel® Cyclone® 10 GX Devices

Feature

Capability

Chip-to-Chip Data Rates

125 Mbps to 12.5 Gbps

Backplane Support Drive backplanes at data rates up to 6.6 Gbps

Optical Module Support

SFP+/SFP, XFP, CXP, QSFP/QSFP28, CFP/CFP2/CFP4

Cable Driving Support

SFP+ Direct Attach, PCI Express over cable, eSATA

Transmit Pre-Emphasis

4-tap transmit pre-emphasis and de-emphasis to compensate for system channel loss

Continuous Time Linear Equalizer (CTLE)

High-gain linear receive equalization to compensate for system channel loss

Variable Gain Amplifier Optimizes the signal amplitude prior to the CDR sampling and operates in fixed and adaptive modes

Precision Signal Integrity Calibration Engine (PreSICE)

Hardened calibration controller to quickly calibrate all transceiver control parameters on power-up, which provides the optimal signal integrity and jitter performance

Advanced Transmit (ATX) PLL

Low jitter ATX (LC tank based) PLLs with continuous tuning range to cover a wide range of standard and proprietary protocols

Fractional PLLs

On-chip fractional frequency synthesizers to replace on-board crystal oscillators and reduce system cost

Digitally Assisted Analog CDR

Superior jitter tolerance with fast lock time

Dynamic Reconfiguration

Allows independent control of the Avalon memory-mapped interface of each transceiver channel for the highest transceiver flexibility

Multiple PCS-PMA and PCS-PLD interface widths

8-, 10-, 16-, 20-, 32-, 40-, or 64-bit interface widths for flexibility of deserialization width, encoding, and reduced latency

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