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1. Integer Arithmetic Intel® FPGA IP Cores
2. LPM_COUNTER (Counter) IP Core
3. LPM_DIVIDE Intel® FPGA IP Core References
4. LPM_MULT (Multiplier) IP Core
5. LPM_ADD_SUB (Adder/Subtractor)
6. LPM_COMPARE (Comparator)
7. ALTECC (Error Correction Code: Encoder/Decoder) IP Core
8. Intel FPGA Multiply Adder IP Core
9. ALTMEMMULT (Memory-based Constant Coefficient Multiplier) IP Core
10. ALTMULT_ACCUM (Multiply-Accumulate) IP Core
11. ALTMULT_ADD (Multiply-Adder) IP Core
12. ALTMULT_COMPLEX (Complex Multiplier) IP Core
13. ALTSQRT (Integer Square Root) IP Core
14. PARALLEL_ADD (Parallel Adder) IP Core
15. Integer Arithmetic Intel® FPGA IP Cores User Guide Document Archives
16. Document Revision History for Integer Arithmetic Intel® FPGA IP Cores User Guide
7.1. ALTECC Encoder Features
7.2. Verilog HDL Prototype (ALTECC_ENCODER)
7.3. Verilog HDL Prototype (ALTECC_DECODER)
7.4. VHDL Component Declaration (ALTECC_ENCODER)
7.5. VHDL Component Declaration (ALTECC_DECODER)
7.6. VHDL LIBRARY_USE Declaration
7.7. Encoder Ports
7.8. Decoder Ports
7.9. Encoder Parameters
7.10. Decoder Parameters
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12.9. Parameters
The following table lists the parameters for the ALTMULT_COMPLEX IP core.
Parameter | IP Generated Parameter | Value | Default Value | Description |
---|---|---|---|---|
General | ||||
How wide should the A input buses be? | WIDTH_A | 1–256 | 18 | Specifies the number of bits for A input buses. |
How wide should the B input buses be? | WIDTH_B | 1–256 | 18 | Specifies the number of bits for B input buses. |
How wide should the ‘result’ output bus be? | WIDTH_RESULT | 1–256 | 36 | Specifies the number of bits for ‘result’ output bus. |
Input Representation | ||||
What is the representation format for A inputs? | REPRESENTATION_A | Signed, Unsigned |
Signed | Specifies the representation format for A inputs. Arria V, Arria® 10, Cyclone V, Cyclone® 10 GX, Stratix® 10, and Stratix V devices support only signed input representation format. |
What is the representation format for B inputs? | REPRESENTATION_B | Signed, Unsigned |
Signed | Specifies the representation format for B inputs. Arria V, Arria® 10, Cyclone V, Cyclone® 10 GX, Stratix® 10, and Stratix V devices support only signed input representation format. |
Complex Multiplier Option | ||||
Dynamic Complex Mode | GUI_DYNAMIC_COMPLEX | — | Unchecked | Enable dynamic switching between 36 x 36 normal mode and 18 x 18 complex mode. Available only in Stratix V devices. |
Implementation Style | ||||
Which implementation style should be used? | IMPLEMENTATION_STYLE | Automatically select a style for best trade-off for the current settings Canonical (Minimize the number of simple multipliers) Conventional (Minimize the use of logic cells) |
Automatically select a style for best trade-off for the current settings | Arria V, Arria® 10, Cyclone V, Cyclone® 10 GX, Stratix® 10, and Stratix V devices support only Automatically select a style for best trade-off for the current settings style. The Quartus® Prime software determines the best implementation based on the selected device family and input width. |
Pipelining (Only available for Arria 10 and Cyclone 10 GX devices) | ||||
Output latency | PIPELINE | 0–11 | 4 | Specifies the number of clock cycles for output latency. |
Create a Clear input? | CLEAR_TYPE | NONE ACLR SCLR |
NONE | Select this option to create aclr or sclr signal for the complex multiplier. |
Create a Clock Enable input? | GUI_USE_CLKEN | — | Unchecked | Select this option to create ena signal for the complex multiplier clock. |