AN 100: In-System Programmability Guidelines

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ID 683546
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. In-System Programmability Guidelines
1. In-System Programmability Guidelines x
1.1. General ISP Guideline 1.2. IEEE Std. 1149.1 Signals 1.3. Sequential versus Concurrent Programming 1.4. ISP Troubleshooting Guidelines 1.5. ISP through Embedded Processors 1.6. ISP through In-Circuit Testers 1.7. Document Revision History
1.1. General ISP Guideline x
1.1.1. Operating Conditions 1.1.2. User Flash Memory Operations During In-System Programming 1.1.3. Interrupting In-System Programming 1.1.4. MultiVolt Devices and Power-Up Sequences 1.1.5. I/O Pins Tri-Stated During In-System Programming 1.1.6. Pull-Up and Pull-Down of JTAG Pins During In-System Programming
1.1.1. Operating Conditions x
1.1.1.1. ISP Voltage 1.1.1.2. Input Voltages
1.2. IEEE Std. 1149.1 Signals x
1.2.1. TCK Signal 1.2.2. Programming Through a Download Cable 1.2.3. Disabling IEEE Std. 1149.1 Circuitry 1.2.4. Working with Different Voltage Levels
1.3. Sequential versus Concurrent Programming x
1.3.1. Sequential Programming 1.3.2. Concurrent Programming 1.3.3. Selecting Sequential or Concurrent Programming 1.3.4. Devices in Different Modes
1.4. ISP Troubleshooting Guidelines x
1.4.1. Invalid ID and Unrecognized Device Messages 1.4.2. Verify the JTAG Chain Continuity 1.4.3. Check the Voltage Levels of the Board During In-System Programming 1.4.4. Random Signals on JTAG Pins 1.4.5. Software Issues
1.5. ISP through Embedded Processors x
1.5.1. Processor and Memory Requirements 1.5.2. Porting the Jam Player
1. In-System Programmability Guidelines

1.1.6. Pull-Up and Pull-Down of JTAG Pins During In-System Programming

An Altera device operating in in-system programming mode require four pins: TDI, TDO, TMS, and TCK. Three of the four JTAG pins have internal weak pull-up or pull-down resistors.

The TDI and TMS pins have internal weak pull-up resistors, while the TCK pin has an internal weak pull-down resistor. However, for device programming in a JTAG chain, there might be devices that do not have internal pull-up or pull-down resistors. Altera recommends to pull the TMS signal high externally through 10-kΩ and the TCK signal low through 1-kΩ resistors. Pulling up the TDI signal externally for the device is optional.

Figure 1. External Pull-Up and Pull-Down Resistors for TMS and TCK of a JTAG Chain in Altera DevicesFigure shows the external pull-up and pull-down for the TMS and TCK pins of the JTAG chain in Altera devices. The TDO pin does not have internal pull-up or pull-down resistors, and does not require external pull-up or pull-down resistors.

The TMS signal is pulled high so that the test access port (TAP) controller remains in the TEST_LOGIC or RESET state even if there is input from TCK signal. During power up, you must pull the TCK signal low to prevent the TCK signal from pulsing high. Pulling the TCK signal high is not recommended because the increase in power supply to the pull-up resistor causes the TCK signal to pulse high; therefore, it is possible for the TAP controller to reach an unintended state.

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