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Definitions
Understanding SSN
Guidelines: Clock and Asynchronous Control Input Signal
Guidelines: Data Input Pin
Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
Guidelines: I/O Restriction Rules
Guidelines: Placement Restrictions for 1.0 V I/O Pin
Guidelines: Analog-to-Digital Converter I/O Restriction
Guidelines: Voltage-Referenced I/O Standards Restriction
Guidelines: Adhere to the LVDS I/O Restrictions Rules
Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers
Guidelines: External Memory Interface I/O Restrictions
Guidelines: ADC Ground Plane Connection
Guidelines: Board Design for ADC Reference Voltage Pin
Guidelines: Board Design for Analog Input
Guidelines: Board Design for Power Supply Pin and ADC Ground (REFGND)
Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2
Document Revision History for Intel® MAX® 10 FPGA Signal Integrity Design Guidelines
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Guidelines: Intel® MAX® 10 Board Design Requirement for DDR2, DDR3, and LPDDR2
- For DDR2, DDR3, and LPDDR2 interfaces, the maximum board skew between pins must be lower than 40 ps. This guideline applies to all pins (address, command, clock, and data).
- To minimize unwanted inductance from the board via, Intel recommends that you keep the PCB via depth for VCCIO banks below 49.5 mil.
- For devices with DDR3 interface implementation, onboard termination is required for the DQ, DQS, and address signals. Intel recommends that you use termination resistor value of 80 Ω to VTT.
- For the DQ, address, and command pins, keep the PCB trace routing length less than six inches for DDR3, or less than three inches for LPDDR2.