Intel® FPGA Temperature Sensor IP Core User Guide

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ID 683585
Date 5/30/2018
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Document Table of Contents x
Intel® FPGA Temperature Sensor IP Core User Guide
Intel® FPGA Temperature Sensor IP Core User Guide x
Intel® FPGA Temperature Sensor Features Intel® FPGA Temperature Sensor Functional Description Using Clear Box Generator Intel® FPGA Temperature Sensor Device Support Intel® FPGA Temperature Sensor Parameters Transfer Function for Internal TSD Intel® FPGA Temperature Sensor IP Core Signals Intel® FPGA Temperature Sensor Prototypes and Component Declarations Document Revision History
Intel® FPGA Temperature Sensor Functional Description x
Temperature Sensing Operation for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices Temperature Sensing Operation for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices
Temperature Sensing Operation for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices x
Generating the Intel® FPGA Temperature Sensor IP Core Example Design Compiling the Intel® FPGA Temperature Sensor IP Core Example Design
Intel® FPGA Temperature Sensor Prototypes and Component Declarations x
Verilog HDL Prototype VHDL Component Declaration
Intel® FPGA Temperature Sensor IP Core User Guide

Intel® FPGA Temperature Sensor IP Core Signals

The following tables list the Intel® FPGA Temperature Sensor IP core signals.
Table 4.   Intel® FPGA Temperature Sensor IP Core Signals for Intel® Arria® 10 and Intel® Cyclone® 10 GX Devices
Signals Direction Width (Bit) Description
corectl Input 1 Enables the temperature sensing feature by the IP core.
reset Input 1 Resets the temperature sensing block.
tempout[9:0] Output 10 Resets the temperature sensing10-bit output data from internal ADC circuitry of temperature sensor block.
eoc Output 1 Indicates end of internal ADC conversion. This signal goes high for one clock cycle of the 1-MHz internal oscillator clock and you can latch the data on tempout at the falling edge of eoc.
Table 5.   Intel® FPGA Temperature Sensor IP Core Signals for Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices
Signals Direction Width (Bit) Description
clk Input 1 Input clock signal that runs at a frequency of 80 MHz and below. The internal clock divider reduces the frequency of the clk signal to 1 MHz or less before clocking the ADC.
ce Input 1 The asynchronous clock enable signal for the clk signal. This signal turns on/off the Intel® FPGA Temperature Sensor IP core that implements the TSD block. This is an active-high signal. By default, this port connects to VCC.
clr Input 1 The asynchronous clear signal. When you assert the clr signal, the IP core sets the tsdcalo[7:0] signal to 11010101 (0xD5) and the tsdcaldone signal to 0. This is an active-high signal. By default, this port connects to GND.
tsdcalo[7:0] Output 8 8-bit output signal that contains the analog-to-digital-conversion temperature value. The 8-bit value maps to a unique temperature value. During device power-up or when you assert the clr signal, the IP core sets the tsdcalo[7:0] to 11010101 (0xD5).
tsdcaldone Output 1 This signal indicates the completion of the temperature sensing process. The IP core asserts this signal when the process is complete. During device power-up or when you assert the clr signal, the IP core sets the tsdcaldone to 0.
Table 6.  The Mapping of tsdcalo[7..0] Value to Arria® V, Arria® V GZ, Stratix® V, and Stratix® IV Devices TemperatureThis table shows the value of tsdcalo[7:0] that corresponds to the device temperature range. The temperature specification ranges from -70° C to 127° C.
Value of tsdcalo[7:0] in Hexadecimal Temperature in Degree Celsius (°C)
FF 127
... ...
E4 100
... ...
D5 85
... ...
D0 80
... ...
B2 50
... ...
9E 30
... ...
8A 10
... ...
80 0
... ...
76 -10
... ...
6C -20
... ...
62 -30
... ...
4E -50
... ...
3A -70° C

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