AN 502: Implementing SMBus Controller in Altera MAX Series

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ID 683635
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Implementing SMBus Controller in Altera MAX Series
1. Implementing SMBus Controller in Altera MAX Series x
1.1. Using a MAX II Device as an SMBus Controller 1.2. Acknowledgments 1.3. Document Revision History
1.1. Using a MAX II Device as an SMBus Controller x
1.1.1. Data Transfer on SMBus 1.1.2. Host Interface 1.1.3. Communicating with the SMBus Controller
1.1.2. Host Interface x
1.1.2.1. Interface Signals 1.1.2.2. Registers 1.1.2.3. Address Register 1.1.2.4. Data Register 1.1.2.5. Status Register
1.1.3. Communicating with the SMBus Controller x
1.1.3.1. Using the Status Register 1.1.3.2. IRQ Signal 1.1.3.3. BUSY Signal
1. Implementing SMBus Controller in Altera MAX Series

1.1.2.4. Data Register

The data register contains the data to be written or read from the SMBDAT line. It is used to transfer the data from the SMBDAT line to the host and vice versa.
Table 4.  Data Register
Bit Name Description
7..0 Data Register SMBus data
Level Two Title