Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Errata

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ID 683637
Date 6/22/2018
Public
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Document Table of Contents x
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Errata
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Errata x
Flash Fallback Does Not Meet PCIe Timeout Unsupported Transaction Layer Packet Types JTAG Timing Failures May Be Reported in the FPGA Interface Manager fpgabist Tool Does Not Pass Hexadecimal Bus Numbers Properly Possible Low dma_afu Bandwidth Due to memcpy Function regress.sh -r Option Does Not Work With dma_afu Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Errata Revision History
Intel® Acceleration Stack for Intel® Xeon® CPU with FPGAs 1.0 Errata

Unsupported Transaction Layer Packet Types

Description

The Acceleration Stack FPGA Interface Manager (FIM) does not support PCIe* Memory Read Lock, Configuration Read Type 1, and Configuration Write Type 1 transaction layer packets (TLPs). If the device receives a PCIe* packet of this type, it does not respond with a Completion packet as expected.

Workaround

No workaround available.

Status

Affects: Intel® Acceleration Stack 1.0 Production

Status: No planned fix

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