AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

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ID 683640
Date 10/14/2019
Public
Document Table of Contents
Document Table of Contents x
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores x
1.1. Fractional PLL Reconfiguration in 28-nm Devices 1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software 1.3. Design Considerations 1.4. Using the Design Examples 1.5. Tutorial Walkthrough 1.6. Document Revision History for AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores
1.1. Fractional PLL Reconfiguration in 28-nm Devices x
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software
1.1.1. Implementing Fractional PLL Reconfiguration on 28-nm Devices Using the Intel® Quartus® Prime Software x
1.1.1.1. Connectivity between Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.2. Connecting Altera PLL and Altera PLL Reconfig IP Cores 1.1.1.3. Avalon-MM Signals in Altera PLL Reconfig IP Core 1.1.1.4. Registers and Counters Settings 1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface 1.1.1.6. .mif Streaming Reconfiguration
1.1.1.4. Registers and Counters Settings x
1.1.1.4.1. Fractional PLL Dynamic Reconfiguration Registers and Settings 1.1.1.4.2. Counter Address and Bit Setting During Read Operation 1.1.1.4.3. Dynamic Phase Shift Counter and cnt_select (Dynamic_Phase_Shift[20:16]) Bit Setting
1.1.1.5. Reconfiguring Fractional PLL Settings with Avalon-MM Interface x
1.1.1.5.1. Waveform Example for Dynamic Reconfiguration with Avalon-MM Interface
1.1.1.6. .mif Streaming Reconfiguration x
1.1.1.6.1. Stitching Two .mif Files Generated by the Intel® Quartus® Prime Software 1.1.1.6.2. .mif Streaming Reconfiguration with Altera PLL Reconfig IP Core 1.1.1.6.3. .mif File Format 1.1.1.6.4. .mif Streaming Reconfiguration Operation Codes
1.2. Fractional PLL Dynamic Phase Shifting in the Intel® Quartus® Prime Software x
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core 1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core
1.2.1. Performing Dynamic Phase Shifting with Altera PLL IP Core x
1.2.1.1. Waveform Example for Dynamic Phase Shift with Altera PLL IP Core 1.2.1.2. Dynamic Phase Shift Signals in Altera PLL IP Core 1.2.1.3. Logical Counter Bit Setting
1.2.2. Performing Dynamic Phase Shifting with Altera PLL Reconfig IP Core x
1.2.2.1. Waveform Example for Dynamic Phase Shift with Altera PLL Reconfig IP Core
1.4. Using the Design Examples x
1.4.1. Software Requirement 1.4.2. Design Example 1: PLL Reconfiguration with Altera PLL Reconfig IP Core to Reconfigure M, N, and C Counters 1.4.3. Design Example 2: PLL Reconfiguration with Altera PLL Reconfig IP Core to Perform Dynamic Phase Shift 1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow 1.4.5. Design Example 4: Dynamic Phase Shift with Altera PLL IP Core 1.4.6. Design Example 5: .mif Streaming Reconfiguration
1.4.4. Design Example 3: PLL Reconfiguration with Altera PLL Reconfig IP Core using Qsys Design Flow x
1.4.4.1. Qsys System and Components 1.4.4.2. Main Menu Commands in Qsys 1.4.4.3. Submenu Commands in Qsys
1.5. Tutorial Walkthrough x
1.5.1. Creating a New Intel® Quartus® Prime Project 1.5.2. Creating the Qsys System 1.5.3. Creating the Top-Level Design File 1.5.4. Incorporating the Nios II SBT for Eclipse 1.5.5. Verifying Design on Hardware
1.5.4. Incorporating the Nios II SBT for Eclipse x
1.5.4.1. Adding Test Code to the Nios II SBT for Eclipse 1.5.4.2. Setting Up the Nios II Project Settings
1.5.5. Verifying Design on Hardware x
1.5.5.1. Compiling the Project 1.5.5.2. Downloading the Object File 1.5.5.3. Verifying Design with the Nios II SBT for Eclipse
1. Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

1.6. Document Revision History for AN 661: Implementing Fractional PLL Reconfiguration with Altera PLL and Altera PLL Reconfig IP Cores

Document Version Changes
2019.10.14 Added a note to the VCO Post Divide Counter Setting register in the Fractional PLL Dynamic Reconfiguration Registers and Settings table.
2019.04.03
  • Changed from "VCO DIV Setting" to "VCO Post Divide Counter Setting", and updated the corresponding counter bit setting in the Fractional PLL Dynamic Reconfiguration Registers and Settings table.
  • Changed instances of Quartus II to Quartus Prime.
2018.11.29 Fixed broken links for design examples and corrected design files filename.
Date Version Changes
May 2016 2016.05.02
  • Updated the description for mgmt_reset signal in Avalon-MM Signals in Altera PLL Reconfig IP Core table.
  • Updated MFRAC equation for M Counter Fractional Value (K) in Fractional PLL Dynamic Reconfiguration Registers and Settings table.
  • Updated MFRAC and C0 counter values in Waveform Example for Dynamic Reconfiguration with Avalon-MM Interface section.
  • Updated design considerations on resynchronizing the fractional PLL using the areset signal.
May 2015 2015.05.04
  • Restructured the document.
  • Added a note on logical counter and physical counter in the Dynamic Phase Shift Signals in Altera PLL IP Core section.
  • Added instructions to stitch two .mif files generated by Quartus® II software with a .tcl script.
  • Added Design Example 5: .mif Streaming Reconfiguration.
August 2014 3.1
  • Changed C_counter[18:22] to C_counter[22:18] in Table 2 on page 4.
November 2013 3.0
  • Added a note to Table 2 on page 4 to clarify that the bypass enable bit, even division bit, and odd division bit of the M, N, C counters support write operation only.
  • Updated Table 2 on page 4 to include VCO DIV setting information.
  • Added “MIF Streaming” on page 12.
  • Changed ALTERA_PLL to Altera PLL as per the naming in the GUI.
  • Changed ALTERA_PLL_RECONFIG to Altera PLL Reconfig as per the naming in the GUI.
  • Added a caution note to “Design Example 4” on page 20 to notify users that the design example is only supported by the Quartus® II software version 13.1 onwards, due to IP upgrade from physical counter to logical counter.
  • Updated “MIF File Format” on page 13 to inform users that they can also construct their own .mif files.
  • Updated Table 2 on page 4 to include MIF Base Address information.
  • Updated Figure 3 on page 9.
  • Updated mgmt_waitrequest information in Table 1 on page 3.
  • Removed Figure 4 on page 11, Figure 5 on page 12, Figure 6 on page 13, Figure 7 on page 14, Figure 8 on page 15, Figure 9 on page 16, and Figure 10 on page 17.
  • Updated “Performing Dynamic Phase Shifting with the Altera PLL IP Core” on page 9 section due to IP upgrade from physical counter to logical counter.
October 2012 2.0
  • Updated “Fractional PLL Reconfiguration in 28-nm Devices” on page 1.
  • Updated Table 1 on page 3, Table 2 on page 4.
  • Added Table 3 on page 6 and Table 10 on page 19.
  • Added Figure 4 on page 11, Figure 5 on page 12, Figure 6 on page 13, Figure 7 on page 14, Figure 8 on page 15, Figure 9 on page 16, Figure 10 on page 17.
  • Added information about performing dynamic phase shifting using the ALTERA_PLL IP core in “Performing Dynamic Phase Shifting with the Altera PLL IP core” on page 9
  • Added new design example and added “Design Example 4” on page 21 for reference.
May 2012 1.1 Updated “Design Considerations” on page 18.
February 2012 1.0 Initial release.
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