Differences Among Intel SoC Device Families

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ID 683648
Date 8/22/2018
Public
Document Table of Contents
Document Table of Contents x
Differences Among Intel SoC Device Families
Differences Among Intel SoC Device Families x
Overview of HPS Modules HPS MPU Subsystem Differences Stratix 10 HPS Interface to SDM Booting and Configuration Differences HPS Cache Coherency Controller Differences HPS System Memory Management Differences HPS On-Chip RAM Differences HPS Error Correction Differences HPS DMA Controller Differences HPS Clock Manager Differences HPS Reset Manager Differences HPS FPGA Manager Differences HPS System Manager Differences HPS Scan Manager Differences HPS Security Feature Differences HPS Interconnect Differences HPS-FPGA Bridge Differences HPS General Purpose I/O Interface Differences HPS I/O Configuration Differences HPS SDRAM Controller Subsystem Differences HPS NAND Flash Controller Differences HPS SD/MMC Controller Differences HPS Quad SPI Flash Controller Differences HPS USB 2.0 OTG Controller Differences HPS EMAC Differences HPS SPI Controller Differences HPS I2C Controller Differences HPS UART Controller Differences HPS CAN Controller Differences HPS Timer Differences HPS Watchdog Timer Differences HPS CoreSight Debug and Trace Differences Document Revision History
Differences Among Intel SoC Device Families

HPS System Memory Management Differences

System Memory Management Feature Cyclone V SoC Arria V SoC Arria 10 SoC Stratix 10 SoC
SMMU implementation None None None ARM MMU-500 r2p0

The Stratix 10 HPS includes a system memory management unit (SMMU) which is responsible for translating virtual addresses to physical addresses. Distributed translation buffer units (TBUs), located between system masters and the L3 interconnect, communicate with the central translation control unit (TCU). The TBUs for the following components accelerate mapping by caching translations:

  • USB
  • Ethernet media access controller (EMAC)
  • NAND controller
  • SD/MMC
  • Embedded trace router (ETR)
  • DMA
  • FPGA-to-HPS bridge

The SMMU allows drivers executing in the MPU to pass virtual addresses directly to peripherals that master memory. This capability reduces driver overhead and complexity, compared to performing virtual-to-physical address translation in software.

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