AN 845: Signal Tap Tutorial for Intel® Arria® 10 Partial Reconfiguration Design

ID 683662
Date 1/28/2022
Public

1.3. Tutorial Design Description

The design for this tutorial consists of one 32-bit counter. At the board level, the design connects the clock to a 50MHz source, and connects the output to four LEDs on the FPGA. Selecting the output from the counter bits in a specific sequence causes the LEDs to blink at a specific frequency.
Figure 2. Flat Reference Design without PR Partitioning