Intel® Stratix® 10 GX FPGA Development Kit User Guide

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ID 683674
Date 4/02/2020
Public
Document Table of Contents
Document Table of Contents x
1. Overview 2. Getting Started 3. Development Board Setup 4. Board Components 5. System Power 6. Board Test System A. Additional Information B. Revision History
1. Overview x
1.1. General Development Board Description 1.2. Recommended Operating Conditions 1.3. Handling the Board
2. Getting Started x
2.1. Installing Intel® Quartus® Prime Software 2.2. Development Board Package 2.3. Installing the Intel® FPGA Download Cable II Driver
2.1. Installing Intel® Quartus® Prime Software x
2.1.1. Activating Your License
3. Development Board Setup x
3.1. Applying Power to the Development Board 3.2. Default Switch and Jumper Settings
4. Board Components x
4.1. Board Overview 4.2. MAX V CPLD System Controller 4.3. FPGA Configuration 4.4. Status Elements 4.5. User Input-Output Components 4.6. Components and Interfaces 4.7. Clock Circuits 4.8. Memory 4.9. Daughtercards
4.5. User Input-Output Components x
4.5.1. User-Defined Push Buttons 4.5.2. User-Defined DIP Switches 4.5.3. User-Defined LEDs
4.6. Components and Interfaces x
4.6.1. PCI Express 4.6.2. 10/100/1000 Ethernet PHY 4.6.3. HiLo External Memory Interface 4.6.4. FMC 4.6.5. QSFP 4.6.6. I2C 4.6.7. DisplayPort 4.6.8. SDI Video Input/Output Ports
4.7. Clock Circuits x
4.7.1. On-Board Oscillators 4.7.2. Off-Board Clock I/O
4.8. Memory x
4.8.1. Flash 4.8.2. Programming Flash using Quartus Programmer
4.9. Daughtercards x
4.9.1. External Memory Interface
4.9.1. External Memory Interface x
4.9.1.1. DDR3L 4.9.1.2. DDR4 4.9.1.3. RLDRAM3 4.9.1.4. QDR-IV 4.9.1.5. FMC Loopback Card
5. System Power x
5.1. Power Guidelines 5.2. Power Distribution System 5.3. Power Measurement 5.4. Thermal Limitations and Protection
6. Board Test System x
6.1. Preparing the Board 6.2. Running the Board Test System 6.3. Using the Board Test System 6.4. Smart VID Setting
6.3. Using the Board Test System x
6.3.1. The Configure Menu 6.3.2. The System Info Tab 6.3.3. The GPIO Tab 6.3.4. The Flash Tab 6.3.5. The XCVR Tab 6.3.6. The PCIe Tab 6.3.7. The FMC Tab 6.3.8. The DDR3 Tab 6.3.9. The DDR4 Tab 6.3.10. Power Monitor 6.3.11. Clock Controller
A. Additional Information x
A.1. Safety and Regulatory Information A.2. Compliance and Conformity Statements
A.1. Safety and Regulatory Information x
A.1.1. Safety Warnings A.1.2. Safety Cautions
1. Overview
2. Getting Started
3. Development Board Setup
4. Board Components
5. System Power
6. Board Test System
A. Additional Information
B. Revision History

4.6.8. SDI Video Input/Output Ports

The Intel® Stratix® 10 GX FPGA development board includes a SDI port, which consists of a M23428G-33 cable driver and a M23544G-14 cable equalizer. The PHY devices from Macom interface to single-ended HDBNC connectors.

The cable driver supports operation from 125 Mbps to 11.88 Gbps. Control signals are allowed for SD and HD modes selections, as well as device enable. The device can be clocked by the 148.5 MHz voltage-controlled crystal oscillator (VCXO) and matched to incoming signals within 50 ppm using the UP and DN voltage control lines to the VCXO.

Table 27.  SDI Video Output Standards for the SD and HD Input
SD_HD Input Supported Output Standards Rise Time
0 SMPTE 424M, SMPTE 292M Faster
1 SMPTE 259M Slower
Table 28.  SDI Video Output Interface Pin Assignments, Schematic Signal Names and Functions
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard
U20.9 SDI_SD_HDn AY40 1.8V
U20.5 SDI_TX_RESET – –
U20.1 SDI_TXCAP_N G46 1.4V PCML
U20.16 SDI_TXCAP_P G47 1.4V PCML
U20.10 SDI_TXDRV_N – –
U20.11 SDI_TXDRV_P – –

The cable equalizer supports operation at 270 Mbit SD, 1.5 Gbit HD and 3.0, 6.0, and 11.88 Gbit dual-link HD modes. Control signals are allowed for bypassing or disabling the device, as well as a carrier detect or auto-mute signal interface.

Table 29.  SDI Cable Equalizer Lengths
Cable Type Data Rate (Mbps) Maximum Cable Length (m)
Belden 1694A 270 400
Belden 1694A 1485 140
Belden 1694A 2970 120
Table 30.  SDI Video Input Interface Pin Assignments, Schematic Signal Names and Functions
Board Reference Schematic Signal Name FPGA Pin Number I/O Standard
U21.10 MF0_BYPASS BA40 1.8V
U21.19 MF1_AUTO_SLEEP BA39 1.8V
U21.21 MF2_MUTE BB39 1.8V
U21.22 MF3_XSD – –
U21.6 MODE_SEL – –
U21.11 MUTEREF – –
U21.4 SDI_EQIN_N1 – –
U21.3 SDI_EQIN_P1 – –
U21.14 SDO_N/SDI_RX_N G42 1.4V PCML
U21.15 SDO_P/SDI_RX_P G43 1.4V PCML
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