AN 837: Design Guidelines for HDMI Intel FPGA IP

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ID 683677
Date 1/28/2019
Public
Document Table of Contents
Document Table of Contents x
1. Design Guidelines for HDMI Intel® FPGA IP 2. Document Revision History for AN 837: Design Guidelines for HDMI Intel® FPGA IP
1. Design Guidelines for HDMI Intel® FPGA IP x
1.1. HDMI Intel® FPGA IP Design Guidelines 1.2. HDMI Intel® FPGA IP Board Design Tips 1.3. Schematic Diagrams 1.4. Hot-Plug Detect (HPD) 1.5. HDMI Intel® FPGA IP Display Data Channel (DDC)
1. Design Guidelines for HDMI Intel® FPGA IP
2. Document Revision History for AN 837: Design Guidelines for HDMI Intel® FPGA IP

1.4. Hot-Plug Detect (HPD)

The HPD signal depends on the incoming +5V Power signal, for example, the HPD pin may be asserted only when the +5V Power signal from the source is detected.

To interface with an FPGA, you need to translate the 5V HPD signal to the FPGA I/O voltage level (VCCIO), using a voltage level translator such as TI TXB0102, which does not have pull-up resistors integrated. An HDMI source needs to pull down the HPD signal so that it can reliably differentiate between a floating HPD signal and a high voltage level HPD signal.

An HDMI sink +5V Power signal must be translated to FPGA I/O voltage level (VCCIO). The signal must be weakly pulled down with a resistor (10K) to differentiate a floating +5V Power signal when not driven by an HDMI source. An HDMI source +5V Power signal has over-current protection of no more than 0.5A.

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