ALTPLL (Phase-Locked Loop) IP Core User Guide

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ID 683732
Date 6/16/2017
Public
Document Table of Contents
Document Table of Contents x
ALTPLL (Phase-Locked Loop) IP Core User Guide
ALTPLL (Phase-Locked Loop) IP Core User Guide x
ALTPLL Features Ports and Parameters Design Examples Document Revision History
ALTPLL Features x
Phase-Locked Loop Types of PLLs Operation Modes Output Clocks Advanced Features PLL Output Counter Cascading
Phase-Locked Loop x
Building Blocks of a PLL PLL Behavior
Types of PLLs x
Parameter Setting Total Number of PLL Available in Each Supported Device Family
Operation Modes x
Operation Modes Supported in Each Device Family Parameter Settings Determining the PLL Lock Range Expanding the PLL Lock Range Setting Up Stratix III and Stratix IV PLLs for LVDS Interfacing Simulating External Feedback Board Delay
Output Clocks x
Parameter Settings Parameter Settings When “Set up PLL in LVDS mode” Option is Enabled Summary of PLL Output Clocks
Advanced Features x
Advanced Control Signals (pllena, areset, pfdena) Clock Switchover Spread-Spectrum Clocking Gated Lock and Self-Reset Programmable Bandwidth Advanced PLL Parameters PLL Dynamic Reconfiguration Dynamic Phase Configuration
Advanced Control Signals (pllena, areset, pfdena) x
pllena areset pfdena Parameter Settings Summary of Advanced Control Signals
Clock Switchover x
Parameter Settings Summary of Automatic Clock Switchover Feature
Spread-Spectrum Clocking x
Parameter Settings Summary of Spread-Spectrum Clocking Feature
Gated Lock and Self-Reset x
Gated Lock Self-Reset on Loss of Lock Parameter Settings Calculating the Value of Gated Lock Counter Summary of Gated Lock Signals and Self-Reset on Loss of Lock
Programmable Bandwidth x
Parameter Settings Summary of Programmable Bandwidth Support
Advanced PLL Parameters x
Advanced Parameter Settings
PLL Dynamic Reconfiguration x
Parameter Settings Summary of Supported Device Families for PLL Dynamic Reconfiguration Feature
Dynamic Phase Configuration x
Supported Devices Parameter Settings Modifying the PLL Phase Shift Step Resolution Using Advanced Parameters
Ports and Parameters x
ALTPLL Input Ports ALTPLL Output Ports ALTPLL Bidirectional Port ALTPLL Parameters
Design Examples x
Design Files Design Example 1: Differential Clock Design Example 2: Generating Clock Signals
Design Example 1: Differential Clock x
Generating a 166-MHz Differential SSTL External Clock Implementing the ddr_clk Design Functional Results — Simulate the ddr_clk Design in the ModelSim®-Altera Software
Design Example 2: Generating Clock Signals x
Generating 133-MHz, 200-MHz, and 200-MHz Time-Shifted Clocks Implementing the shift_clk Design Simulating the shift_clk Design in the ModelSim-Altera Software
ALTPLL (Phase-Locked Loop) IP Core User Guide

Document Revision History

Date Version Changes Made
June 2017 2017.06.16
  • Added support for Cyclone® 10 LP devices.
  • Changed instances of Quartus II to Quartus Prime.
April 2015 2015.04.17
  • Added restriction on self-reset for PLL reconfiguration in the PLL Dynamic Reconfiguration section.
  • Removed the topics about the IP catalog and parameter editor, generating IP cores, and the files generated by the IP core, and added links to IP documents.
August 2014 2014.08.18
  • Updated parameterization steps for legacy parameter editor.
  • Added note that this IP core does not support Arria 10 designs.
June 2014 2014.06.30
  • Replaced MegaWizard Plug-In Manager information with IP Catalog.
  • Added standard information about upgrading IP cores.
  • Added standard installation and licensing information.
  • Removed outdated device support level information. IP core device support is now available in IP Catalog and parameter editor.
  • Updated description in Operation Modes section.
  • Added Cyclone IV device in PLL Dynamic Reconfiguration Feature Support table.
  • Updated the Advanced Control Signals summary table.
August 2013 2013.08.22 Added a link to AN454: Implementing PLL Reconfiguration in Stratix III and Stratix IV Devices.
May 2013 9.0 DITA conversion.
November 2009 8.0 Updated to reflect new document organization and format.
December 2008 7.0
  • Updated the following sections:
  • “Device Family Support” section
  • “Introduction” section
  • “Features” section
  • “General Description” section
  • “Design Examples” section
  • “Simulation” section
  • “Ports and Parameters” section
  • “How to Contact Altera” section
  • Removed the following sections:
  • “Resource Utilization & Performance” section
  • “Software and System Requirements” section
  • “Instantiating Multifunction in HDL Code” section
  • “Identifying a Multifunction after Compilation” section
  • “Signature II Embedded Logic Analyzer” section
  • Reorganized the “Using the MegaWizard Plug-In Manager” section into table format.
  • Renamed “About this User Guide” section to “Additional Information” and moved the section to the end of the user guide.
March 2007 6.0 Updated for software version 7.0, including:
  • Added support for Cyclone III devices
  • Added Referenced Documents section
December 2006 5.0 Updated to reflect new document organization, additions, and GUI changes for Quartus 6.1, including adding information relating to Stratix III devices
May 2006 4.0 Updated to reflect new document organization, additions, and GUI changes for Quartus 6.0
December 2004 3.0 Updated to reflect new document organization and GUI changes
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