ALTDQ_DQS2 IP Core User Guide

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ID 683742
Date 5/08/2017
Public
Document Table of Contents
Document Table of Contents x
ALTDQ_DQS2 IP Core User Guide
ALTDQ_DQS2 IP Core User Guide x
ALTDQ_DQS2 Features ALTDQ_DQS2 Device Support Resource Utilization and Performance ALTDQ_DQS2 Parameter Settings ALTDQ_DQS2 Data Paths ALTDQ_DQS2 Ports Dynamic Reconfiguration for ALTDQ_DQS2 Stratix V Design Example Arria V Design Example IP-Generate Command ALTDQ_DQS2 IP Core User Guide Archives Document Revision History
ALTDQ_DQS2 Data Paths x
DQ and DQS Input Path DQ and DQS Output Path
DQ and DQS Input Path x
DQ and DQS Input Paths for Stratix V Devices Data Input Path for Arria V, Cyclone V, and Stratix V Devices Blocks in DQ and DQS Data Input Path
Blocks in DQ and DQS Data Input Path x
DQS Logic Capture DDIO to Read FIFO Path FIFO Control
DQ and DQS Output Path x
DQ and DQS Output Path for Stratix V Devices Blocks in DQ and DQS Output Path DQ and DQS Output Path for Arria V and Cyclone V Devices
ALTDQ_DQS2 Ports x
ALTDQ_DQS2 Data Strobe Ports ALTDQ_DQS2 Data Ports ALTDQ_DQS2 Termination Control Ports ALTDQ_DQS2 PLL and DLL Ports ALTDQ_DQS2 Hard FIFO Ports ALTDQ_DQS2 Dynamic Configuration Ports
Dynamic Reconfiguration for ALTDQ_DQS2 x
I/O Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices DQS Configuration Block Bit Sequence for Arria V GZ and Stratix V Devices I/O Configuration Block Bit Sequence for Arria V and Cyclone V Devices DQS Configuration Block Bit Sequence for Arria V and Cyclone V Devices Example Usage of Dynamic Reconfiguration for ALTDQ_DQS2
Stratix V Design Example x
Instantiating ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Stratix V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Stratix V Design Example x
Dynamic Configuration SDC Walkthrough
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results
DQS Read Operation x
DQS Delay Chain Hard Read FIFO
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe
Arria V Design Example x
Instantiating the ALTDQ_DQS2 IP Core Instantiating the ALTDLL IP Core Instantiating ALT_OCT IP Core Instantiating Altera PLL Setting Up NativeLink and Simulation Settings Understanding Simulation Results—Arria V Design Example
Instantiating Altera PLL x
Altera PLL Clock Settings Information
Understanding Simulation Results—Arria V Design Example x
Dynamic Configuration
Dynamic Configuration x
DQS Write Operation Side Read Operation Side Write Operation DQS Read Operation Simulation Results SDC Walkthrough
DQS Read Operation x
DQS Delay Chain VFIFO, LFIFO, and Read FIFO DQS Enable Control
SDC Walkthrough x
Analyzing Same Edge Transfer Constraining Outgoing DQS Strobe Timing Violation tq_analysis.tcl
IP-Generate Command x
Using IP-Generate Command
ALTDQ_DQS2 IP Core User Guide

Using IP-Generate Command

You can use ip-generate.exe, a command-line executable, to configure parameters. The command creates or modifies custom IP core variations, which you can then instantiate in a design file.

To run the ip-generate command, follow these steps:

  1. Locate the ip-generate.exe executable file in the <quartus_install_dir>\quartus\sopc_builder\bin folder. Ensure that you include the directory path into your operating system environment.
  2. To obtain the options for the ip-generate command, type the following command in the command prompt: 
    ip-generate –help
  3. To instantiate the IP core using the executable file, type the following syntax: 
    ip-generate --component-name=altdq_dqs2 -–component-system-param=DEVICE_FAMILY=”Stratix V” -–file-set=QUARTUS_SYNTH --output-name[=<file_name>] –-component- param[=<parameter_name>][=<parameter_value>]
    The <file_name> is the instance name. For example, my_dqdqs2. The <parameter_name> is the name of the parameter that you configure with the value stated in <parameter_value>.

    You must use the –-component-param[=<parameter_name>][=<parameter_value>] option for every parameter assignment. Parameters that are not assigned take the default values. Ensure that you type the exact case and spaces for the parameter names and values.

    The following list describes two examples of how you can use this command:

    • To create an ALTDQ_DQS2 instance named my_dqdqs2 with all the default parameter values, type the following command: 
    ip-generate --component-name=altdq_dqs2 -–component-system-param=DEVICE_FAMILY=”Stratix V” --output-name=my_dqdqs2 -–file-set=QUARTUS_SYNTH
    • To create an ALTDQ_DQS2 instance named mydq_dqs2 without output strobe ports, and with a 135° DQS phase shift, type the following command: 
    ip-generate --component-name=altdq_dqs2 –-component-system-param=DEVICE_FAMILY=”Stratix V” --output-name=my_dqdqs2 -–file-set=QUARTUS_SYNTH --component-param=USE_OUTPUT_STROBE=”False” --component-param=DQS_PHASE_SETTING=”3”

    This command generates two files—my_dqdqs2.v and my_dqdqs2_altdq_dqs2.sv. The my_dqdqs2.v file contains the my_dqdqs2 top level module, and the my_dqdqs2_altdq_dqs2.sv file contains the source code. The files are in Verilog HDL format.

    The ip-generate command generates the ports for the instance based on the parameter values.

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