Intel® MAX® 10 General Purpose I/O User Guide

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ID 683751
Date 10/31/2022
Public
Document Table of Contents
Document Table of Contents x
1. Intel® MAX® 10 I/O Overview 2. Intel® MAX® 10 I/O Architecture and Features 3. Intel® MAX® 10 I/O Design Considerations 4. Intel® MAX® 10 I/O Implementation Guides 5. GPIO Lite Intel® FPGA IP References 6. Intel® MAX® 10 General Purpose I/O User Guide Archives 7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide
1. Intel® MAX® 10 I/O Overview x
1.1. Intel® MAX® 10 Devices I/O Resources Per Package 1.2. Intel® MAX® 10 I/O Vertical Migration Support
2. Intel® MAX® 10 I/O Architecture and Features x
2.1. Intel® MAX® 10 I/O Standards Support 2.2. Intel® MAX® 10 I/O Elements 2.3. Intel® MAX® 10 I/O Buffers 2.4. I/O Standards Termination
2.1. Intel® MAX® 10 I/O Standards Support x
2.1.1. Intel® MAX® 10 I/O Standards Voltage and Pin Support
2.2. Intel® MAX® 10 I/O Elements x
2.2.1. Intel® MAX® 10 I/O Banks Architecture 2.2.2. Intel® MAX® 10 I/O Banks Performance 2.2.3. Intel® MAX® 10 I/O Banks Locations
2.3. Intel® MAX® 10 I/O Buffers x
2.3.1. Schmitt-Trigger Input Buffer 2.3.2. Programmable I/O Buffer Features
2.3.2. Programmable I/O Buffer Features x
2.3.2.1. Programmable Open Drain 2.3.2.2. Programmable Bus Hold 2.3.2.3. Programmable Pull-Up Resistor 2.3.2.4. Programmable Current Strength 2.3.2.5. Programmable Output Slew Rate Control 2.3.2.6. Programmable IOE Delay 2.3.2.7. PCI Clamp Diode 2.3.2.8. Programmable Pre-Emphasis 2.3.2.9. Programmable Differential Output Voltage 2.3.2.10. Programmable Emulated Differential Output 2.3.2.11. Programmable Dynamic Power Down
2.4. I/O Standards Termination x
2.4.1. Voltage-Referenced I/O Standards Termination 2.4.2. Differential I/O Standards Termination 2.4.3. Intel® MAX® 10 On-Chip I/O Termination
2.4.3. Intel® MAX® 10 On-Chip I/O Termination x
2.4.3.1. OCT Calibration 2.4.3.2. RS OCT in Intel® MAX® 10 Devices
3. Intel® MAX® 10 I/O Design Considerations x
3.1. Guidelines: VCCIO Range Considerations 3.2. Guidelines: Voltage-Referenced I/O Standards Restriction 3.3. Guidelines: Enable Clamp Diode for LVTTL/LVCMOS Input Buffers 3.4. Guidelines: Adhere to the LVDS I/O Restrictions Rules 3.5. Guidelines: I/O Restriction Rules 3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin 3.7. Guidelines: Analog-to-Digital Converter I/O Restriction 3.8. Guidelines: External Memory Interface I/O Restrictions 3.9. Guidelines: Dual-Purpose Configuration Pin 3.10. Guidelines: Clock and Data Input Signal for Intel® MAX® 10 E144 Package
3.6. Guidelines: Placement Restrictions for 1.0 V I/O Pin x
3.6.1. Calculating the Total Inductance for 1.0 V Pin Placement
4. Intel® MAX® 10 I/O Implementation Guides x
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP 4.2. Verifying Pin Migration Compatibility
4.1. GPIO Lite Intel FPGA IP GPIO Lite Intel® FPGA IP x
4.1.1. GPIO Lite Intel® FPGA IP Data Paths
4.1.1. GPIO Lite Intel® FPGA IP Data Paths x
4.1.1.1. DDR Input Path 4.1.1.2. DDR Output Path with Output Enable
5. GPIO Lite Intel® FPGA IP References x
5.1. GPIO Lite Intel® FPGA IP Parameter Settings 5.2. GPIO Lite Intel® FPGA IP Interface Signals
1. Intel® MAX® 10 I/O Overview
2. Intel® MAX® 10 I/O Architecture and Features
3. Intel® MAX® 10 I/O Design Considerations
4. Intel® MAX® 10 I/O Implementation Guides
5. GPIO Lite Intel® FPGA IP References
6. Intel® MAX® 10 General Purpose I/O User Guide Archives
7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide

7. Document Revision History for Intel® MAX® 10 General Purpose I/O User Guide

Document Version Intel® Quartus® Prime Version Changes
2022.10.31 22.1
  • Updated the list of Intel® MAX® 10 device packages that support the 1.0 V LVCMOS I/O standard.
  • Added 1.8 V LVDS I/O standard support.
  • Updated the spreadsheet files (max10-1v-mutual-coupling.zip) that list the mutual inductance values for 1.0 V I/O.
2022.01.27 21.1 Updated the spreadsheet files (max10-1v-mutual-coupling.zip) that list the mutual inductance values for 1.0 V I/O.
2021.11.01 21.1
  • Added V81 and Y180 packages in the Package Plan for Intel® MAX® 10 Single Power Supply Devices table.
  • Added Y180 package in the Migration Capability Across Intel® MAX® 10 Devices diagram.
  • Updated footnote for 1.0 V LVCMOS to include new devices in the Supported I/O Standards in Intel® MAX® 10 Devices table.
  • Updated figure title to I/O Banks for 10M02 (Single Power Supply U324 Package), 10M04, and 10M08 (Except V81, M153, and U169 Packages) Devices.
  • Added diagram: I/O Banks for 10M08 V81, M153, and U169 Packages Devices.
  • Updated max10-1v-mutual-coupling.zip file and the link description to include new devices.
  • Added F256 device package and updated U324 device package in the DDR3 and LPDDR2 Memory Interface Widths and Device Packages Where Two GPIOs Adjacent to DQ Pins Are Disabled table.
2021.04.27 20.1 Updated the guidelines in the table listing the geometry-based I/O restrictions related to ADC usage.
2020.11.05 20.1 Updated the guidelines for JTAG pins in table Dual-Purpose Configuration Pin Guidelines for Intel MAX 10 Devices.
2020.09.22 20.1 Updated the clamp diode for LVTTL/LVCMOS input buffers guidelines to remove references to "undershoot". The clamp diode manages overshoot voltages only.
2020.08.24 20.1 Updated the table in the I/O restriction rules guideline topic to improve clarity.
2020.06.30 20.1
  • Added support for 1.0 V LVCMOS I/O standard.
  • Added placement restriction guideline for 1.0 V I/O pins.
2019.01.01 18.1 Removed support for 1.0 V LVCMOS I/O standard.
2018.12.20 18.1
  • Updated introductory statements about GPIO usage to improve clarity.
  • Added support for 1.0 V LVCMOS I/O standard for commercial grade devices only.
  • Added link to the list of Intel® MAX® 10 develoment kits and boards.
  • Added statement to clarify that when the Intel® MAX® 10 device is blank or erased, the I/Os are tri-stated.
  • Updated the guideline for VCCIO range to improve clarity.
  • Updated the topic about the PCI clamp diode and added links to related information.
  • Updated the topic about programmable emulated differential output to improve clarity.
Date Version Changes
December 2017 2017.12.15
  • Added the U324 package for the Intel® MAX® 10 single power supply devices.
  • Updated the I/O vertical migration figure.
  • Added a topic about the different I/O banks performance.
  • Updated the GPIO Lite DDR output path figure, timing diagram, and added descriptions to improve clarity.
  • Updated the description in the guideline topic about I/O restrictions to improve clarity.
  • Updated the guideline topic about the clock and data input signal for the E144 package to improve clarity.
  • Updated the guideline topic about the ADC I/O restriction to clarify that the guidelines are geometry-based rules for design estimation purpose.
  • Removed all "Preliminary" markers.
  • Updated the topic about the PCI clamp diode to remove the sentence that mention the active serial (AS) configuration scheme. Intel® MAX® 10 devices do not support the AS configuration scheme.
  • Updated the guideline topic about enabling the clamp diode for the LVTTL/LVCMOS input buffers to improve clarity.
February 2017 2017.02.21 Rebranded as Intel.
May 2016 2016.05.02
  • Updated the list of supported I/O standards to specify I/O standards that are supported only in dual power supply Intel® MAX® 10 devices.
  • Updated the names of emulated differential I/O standards to improve clarity.
  • Updated the topic about the I/O standards voltage and pin support to clarify that the I/O standards that a pin type supports depends on pin's I/O bank.
  • Updated the setting information for PCI clamp diode:
    • On by default for input pins for all supported I/O standards
    • Off by default for output pins for all supported I/O standards, except 3.0 V PCI
  • Updated the topic about the ADC I/O restriction:
    • Added the list of devices with physics-based rules support from Intel® Quartus® Prime version 15.0.1.
    • Clarified that the table listing the percentage of GPIOs allowed in bank 8 is an example for the F484 package. For all packages, the Intel® Quartus® Prime software displays a warning message if you exceed the allowed GPIO percentage.
November 2015 2015.11.02
  • Added PCI clamp diode support for the 3.3 V and 2.5 V Schmitt Trigger I/O standards.
  • Added a table that summarizes the programmable I/O buffer features and settings.
  • Updated the topics about VCCIO range consideration and VREF I/O standards restriction with guidelines for using different VCCIO supplies in bank 1A and bank 1B.
  • Added guidelines topic about using the clock and input pins in the E144 package.
  • Added the Enable nsleep port parameter option.
  • Removed the topics about the IP catalog and parameter editor, generating IP cores, and the files generated by the IP core, and added a link to Introduction to Intel IP Cores.
  • Changed instances of Quartus II to Quartus Prime.
June 2015 2015.06.10
  • Added related link to the Intel® MAX® 10 device pin-outs in topic about I/O banks locations. The device pin-out files provide more information about available I/O pins in each I/O bank.
  • Updated the ADC I/O restriction guidelines topic.
May 2015 2015.05.04
  • Removed the F672 package of the Intel® MAX® 10 10M25 device.
  • Updated footnote for LVDS (dedicated) in the table listing the supported I/O standards to clarify that you can use LVDS receivers on all I/O banks.
  • Added missing footnote number for the DQS column of the 3.3 V Schmitt Trigger row in the table that lists the I/O standards voltage levels and pin support.
  • Added a table listing the I/O standards and current strength settings that support programmable output slew rate control.
  • Updated the topic about external memory interface I/O restrictions to add x24 memory interface width to the F484 package.
  • Added topic about the programmable differential output voltage.
  • Updated the guidelines for voltage-referenced I/O standards to add a list of device packages that do not support voltage-referenced I/O standards.
  • Updated the topic about the I/O restriction rules to remove statements about the differential pad placement rules.
  • Renamed the input_ena signal name to nsleep and updated the relevant description.
  • Updated the description for the Invert DDIO inclock parameter of the GPIO Lite IP core.
December 2014 2014.12.15 Updated the topic about the ADC I/O restriction:
  • Added information about implementation of physics-based rules in the Intel® Quartus® Prime software.
  • Updated the list of I/O standards groups for the ADC I/O restriction.
September 2014 2014.09.22 Initial release.
Level Two Title