JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

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ID 683758
Date 10/14/2022
Public
Document Table of Contents
Document Table of Contents x
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide x
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide 1.2. Design Example Detailed Description 1.3. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide Archives 1.4. Document Revision History for the JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide
1.1. JESD204B Intel® Stratix® 10 FPGA IP Design Example Quick Start Guide x
1.1.1. Directory Structure 1.1.2. Generating the Design 1.1.3. Simulating the Design 1.1.4. Compiling and Testing the Design
1.1.2. Generating the Design x
1.1.2.1. Design Example Parameters
1.1.4. Compiling and Testing the Design x
1.1.4.1. Board Connectivity 1.1.4.2. Hardware Test for System Console Control Design Example
1.2. Design Example Detailed Description x
1.2.1. Features 1.2.2. Hardware and Software Requirements 1.2.3. Supported Configurations 1.2.4. Presets 1.2.5. Functional Description 1.2.6. Simulation 1.2.7. Design Example Files 1.2.8. Registers 1.2.9. Signals 1.2.10. Customizing the Design Example
1.2.5. Functional Description x
1.2.5.1. Platform Designer System Component 1.2.5.2. Transport Layer 1.2.5.3. Test Pattern Generator 1.2.5.4. Test Pattern Checker 1.2.5.5. Clocking Scheme
1.2.6. Simulation x
1.2.6.1. Testbench
1.2.10. Customizing the Design Example x
1.2.10.1. Modifying the JESD204B IP Core Parameters 1.2.10.2. Changing the Data Rate or Reference Clock Frequency
1. JESD204B Intel® Stratix® 10 FPGA IP Design Example User Guide

1.2.5. Functional Description

The design example consists of various components.

The following block diagram shows the design components and the top-level signals of the design example.

Figure 9. JESD204B Design Example Block Diagram
  • Platform Designer system
    • JESD204B subsystem
    • JTAG to Avalon master bridge—For System Console Control design example only
    • Parallel I/O (PIO)
    • ATX PLL (Applicable only for Intel® Stratix® 10 L-tile and H-tile devices)
    • Core PLL
    • Serial Port Interface (SPI)—master module
  • Test pattern generator (For duplex and simplex TX data path only)
  • Test pattern checker (For duplex and simplex RX data path only)
  • Assembler—TX transport layer (For duplex and simplex TX data path only)
  • Deassembler—RX transport layer (For duplex and simplex RX data path only)

Section Content
Platform Designer System Component
Transport Layer
Test Pattern Generator
Test Pattern Checker
Clocking Scheme

Level Two Title