AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

Download PDF
ID 683778
Date 3/15/2024
Public
Document Table of Contents
Document Table of Contents x
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design 2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design 3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design 4. Functionality Level and Resource Utilization Estimates 5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design 6. Document Revision History for the AN 896: Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design x
1.1. Features of the Reference Design 1.2. Structure of the Reference Design Archive
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design x
2.1. Reference Design Architecture 2.2. Reference Design Component Blocks 2.3. Design Components and Parameter Options 2.4. Output Voltage Data Formats and Related Parameters
2.3. Design Components and Parameter Options x
2.3.1. Reset Sequencer (Reset_Sequencer) 2.3.2. Modular ADC Core Intel® FPGA IP (ADC_Core) 2.3.3. Sequencer ADC Decoder (ADC_Decoder) 2.3.4. Sequencer Voltage Monitor (Sequencer_VMonitor) 2.3.5. PMBus* Slave to Avalon®-MM Master Bridge (PMBus_Slave) 2.3.6. Power Sequencer (Sequencer_Core) 2.3.7. Other Design Components
2.3.3. Sequencer ADC Decoder (ADC_Decoder) x
2.3.3.1. Sequencer ADC Decoder Parameter Settings
2.3.4. Sequencer Voltage Monitor (Sequencer_VMonitor) x
2.3.4.1. Sequencer Voltage Monitor Parameter Settings
2.3.6. Power Sequencer (Sequencer_Core) x
2.3.6.1. Power Sequencer Parameter Settings
2.3.7. Other Design Components x
2.3.7.1. POR Pulse (POR_Pulse) 2.3.7.2. Reset to Conduit Adapter (Reset2Conduit) 2.3.7.3. pll_lock_splitter (PLL_LockSplit) 2.3.7.4. Avalon®-MM Sequencer (AVMM_Initializer)
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design x
3.1. Customizing and Generating the Design Example 3.2. Updating the Schematic After Customizing the Design 3.3. Assigning Pins and Compiling the Design Example 3.4. Testbench Simulation to Understand Design Behavior
3.3. Assigning Pins and Compiling the Design Example x
3.3.1. Pin Description
3.4. Testbench Simulation to Understand Design Behavior x
3.4.1. Generating the Testbench Simulation 3.4.2. Running the Testbench Simulation
4. Functionality Level and Resource Utilization Estimates x
4.1. PMBus* Commands Implementation 4.2. Resource Utilization of the Multi-Rail Power Sequencer and Monitor Reference Design
1. Overview of the Multi-Rail Power Sequencer and Monitor Reference Design
2. Architecture and Operation of the Multi-Rail Power Sequencer and Monitor Reference Design
3. Implementation and Simulation of the Multi-Rail Power Sequencer and Monitor Reference Design
4. Functionality Level and Resource Utilization Estimates
5. PCB Implementation for the Multi-Rail Power Sequencer and Monitor Reference Design
6. Document Revision History for the AN 896: Multi-Rail Power Sequencer and Monitor Reference Design

2.3.6.1. Power Sequencer Parameter Settings

There are three groups of options: Parameters, Sequencer Setup, and Parameters (delay settings).
Table 5.   Power Sequencer Parameters
Parameter Description
Output Voltage Rails

Specify the number of output voltage rails to sequence.

The number must match the value you specify in the other components of the system. Otherwise, the interface bus widths between components will not match.

Combine rails into groups

Turn on to group power rails with common enable signals and logically AND the individual power good status signals.
Number of Power Groups

Specify the number of power groups for the sequencer to implement.

The sequencer creates one set of enable/discharge outputs per group.

Note: This option is available if you turn on Combine rails into groups.
Component’s Clock Frequency

Read-only parameter that specifies the component's input clock frequency.

  • The number depends on which clock you connect to the component in the Platform Designer.
  • Ensure that this frequency is correct. Otherwise, the system cannot derive the correct delay values.
Use Open-drain Outputs

Controls whether open-drain or push-pull drivers are used for nFAULT, VRAIL_ENA, and VRAIL_DCHG.

The default is to use open-drain outputs which drive to the VCCIO rail when active and tri-state (with external pull-down) when inactive. Using open-drain eliminates the potential of glitching these outputs during configuration and before they are actively driven by the CPLD. For standard push-pull outputs or to utilize a different output type, uncheck this box.

Table 6.   Power Sequencer Parameters - Sequencer SetupYou can specify the time units in s, ms, us (for µs), and ns. For example, specify 10us for a 10 µs delay.
Parameter Description
Sequencer Delay (PG to next OE)

Specify the delay:

  • From the moment the master enable signal asserts before the output enable signal asserts; or
  • From the moment power good asserts until the next rail's or group's output enable signal asserts.

Specify 0ns to bypass the delay.

Qualification Window (OE to PG)

Specify the qualification window for which power good must assert after output enable is asserted.

If the qualification time violation occurs, the component indicates a fault and sequences the power rails down (in reverse order of the power up).

Power Group Number

Specify which power group (starting from 0) to assign the rail.

  • For all rails with the same group number, use the same enable/discharge signal.
  • The design evaluates the power good signals of the rails in the same group together (ANDed).
Table 7.   Power Sequencer Parameters - Parameters (Delay Settings)You can specify the time units in s, ms, us (for µs), and ns. For example, specify 10us for a 10 µs delay.
Parameter Description
Delay Time Between Restarts Specify the delay interval between restart attempts for the sequencer. All power good signals must be low before the delay counter is started.
Maximum Specified Delay in Table Above

Read-only value that displays the derived maximum delay from all parameters.

The component passes the value to the design to size the counters accurately .

Level Two Title