AN 744: Scalable Triple Speed Ethernet Reference Design for Arria 10 Devices

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ID 683785
Date 5/13/2016
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Document Table of Contents
Document Table of Contents x
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices x
1.1. Block Diagrams 1.2. Design Components 1.3. Design Parameters 1.4. Hardware and Software Requirements 1.5. Using the Reference Design 1.6. Upgrading the Components 1.7. Testbench 1.8. Interface Signals 1.9. Configuration Registers 1.10. Document Revision History
1.7. Testbench x
1.7.1. Testbench Files 1.7.2. Simulating the Testbench 1.7.3. Test Case: Design With the IEEE 1588v2 Feature 1.7.4. Test Case: Design Without the IEEE 1588v2 Feature
1.8. Interface Signals x
1.8.1. Packet Classifier Interface Signals 1.8.2. ToD Interface Signals
1.9. Configuration Registers x
1.9.1. ToD Registers 1.9.2. Packet Generator Registers 1.9.3. Traffic Monitor Registers
1. AN-744: Scalable Triple Speed Ethernet Reference Designs for Arria 10 Devices

1.7.4. Test Case: Design Without the IEEE 1588v2 Feature

The simulation performs the following steps.

  1. Starts up the design with an operating speed of 1 Gbps.
  2. Configures the MAC, PHY speed, and FIFO buffer for the channels.
  3. Waits until the design asserts the channel_ready signal for each channel.
  4. Sends the following packets:
    • Basic data frame, 64 bytes.
    • VLAN multicast data frame, 1000 bytes.
    • Basic data frame, 800 bytes.
    • SVLAN broadcast data frame, 80 bytes.
    • VLAN unicast data frame, 500 bytes.
    • SVLAN data frame, 1500 bytes.
  5. Repeats steps 2 to 4 for operating speeds 100 Mbps and 10 Mbps.

When simulation ends, the values of the MAC statistics counters are displayed in the transcript window. The transcript window also displays PASSED if the RX Avalon-ST interface of channel 0 received all packets successfully.

Figure 6. Simulation Results
Level Two Title