AN 500: NAND Flash Memory Interface with Altera MAX Series

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ID 683829
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. NAND Flash Memory Interface with Altera MAX Series
1. NAND Flash Memory Interface with Altera MAX Series x
1.1. NAND Flash Interface Using Altera Devices 1.2. Implementation 1.3. Acknowledgments 1.4. Document Revision History
1.1. NAND Flash Interface Using Altera Devices x
1.1.1. Signals 1.1.2. Operations 1.1.3. AMD and Samsung NAND Flash Devices Commands
1.2. Implementation x
1.2.1. Source Code
1. NAND Flash Memory Interface with Altera MAX Series

1.3. Acknowledgments

Design example adapted for Altera MAX 10 FPGAs by:

Orchid Technologies Engineering and Consulting, Inc.

Maynard, Massachusetts 01754

TEL: 978-461-2000

WEB: www.orchid-tech.com

EMAIL: info@orchid-tech.com

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