F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

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ID 709308
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Intel® FPGA IP Design Examples 3. HDCP Over DisplayPort Design Example 4. Document Revision History for F-Tile DisplayPort Intel® FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. DisplayPort Intel® FPGA IP Design Examples x
2.1. Agilex™ 7 F-Tile DisplayPort SST Parallel Loopback Design Features 2.2. Agilex™ 7 F-Tile DisplayPort SST TX-only Design Features 2.3. Agilex™ 7 F-Tile DisplayPort SST RX-only Design Features 2.4. Design Components 2.5. Clocking Scheme 2.6. Interface Signals and Parameters
3. HDCP Over DisplayPort Design Example x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios® V Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Setting Up the Hardware 3.4.2. Generating the Design 3.4.3. Including HDCP Production Keys 3.4.4. Compiling the Design 3.4.5. Viewing the Results
3.4.3. Including HDCP Production Keys x
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Intel® FPGA IP Design Examples
3. HDCP Over DisplayPort Design Example
4. Document Revision History for F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

1.3. Generating the Design

Use the DisplayPort Intel® FPGA IP parameter editor in Quartus® Prime software to generate the design example.
Note: You need a Nios® V evaluation license. Refer to the Nios® V Processor Licensing topic in the Nios® V Embedded Processor Design Handbook.
Figure 3. Generating the Design Flow
  1. To generate an example design, follow these steps:
    • For Quartus® Prime Pro Edition running in a Windows environment:
      1. Open " Nios® V Command Shell" from the Windows search path.
      2. Run "quartus" in Nios® V Command Shell to open Quartus® Prime Pro Edition.
    • For Quartus® Prime Pro Edition running in a Linux environment:
      1. cd to <Quartus installation path>/niosv/bin and run "niosv-shell".
      2. Run "quartus" to open Quartus® Prime Pro Edition.
  2. Select Tools > IP Catalog, and select Agilex™ 7 F-Tile as the target device family.
    Note: The design example only supports Agilex™ 7 F-Tile devices.
  3. In the IP Catalog, locate and double-click DisplayPort Intel FPGA IP. The New IP Variation window appears.
  4. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  5. Select an Agilex™ 7 F-Tile device in the Device field, or keep the default Quartus® Prime software device selection.
  6. Click OK. The parameter editor appears.
  7. Configure the desired parameters for both TX and RX.
    Note: The Nios® V software has the capability to read and print out the DisplayPort Main Stream Attribute (MSA) information in the Nios® V terminal. To read or print the MSA information, turn on the Enable GPU Control parameter.
  8. Under the Design Example tab, select DisplayPort SST Parallel Loopback Without PCR, DisplayPort SST Parallel Loopback with AXIS Video Interface, DisplayPort SST TX-only, or DisplayPort SST RX-only.
  9. Select Synthesis to generate the hardware design example.
  10. For Target Development Kit, select Agilex™ 7 I-Series SoC Development Kit FA or Agilex™ 7 I-Series SoC Development Kit FB. This causes the target device selected in step 4 to change to match the device on the development kit.
    • For Agilex™ 7 I-Series SoC Development Kit FA, the default device is AGIB027R31B1E1V.
    • For Agilex™ 7 I-Series SoC Development Kit FB, the default device is AGIB027R31B1E1VAA.
  11. Click Generate Example Design.
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