F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

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ID 709308
Date 4/09/2024
Public
Document Table of Contents
Document Table of Contents x
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide 2. DisplayPort Intel® FPGA IP Design Examples 3. HDCP Over DisplayPort Design Example 4. Document Revision History for F-Tile DisplayPort Intel® FPGA IP Design Example User Guide
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide x
1.1. Directory Structure 1.2. Hardware and Software Requirements 1.3. Generating the Design 1.4. Simulating the Design 1.5. Compiling and Testing the Design 1.6. DisplayPort Intel® FPGA IP Design Example Parameters
1.5. Compiling and Testing the Design x
1.5.1. Regenerating ELF File
2. DisplayPort Intel® FPGA IP Design Examples x
2.1. Agilex™ 7 F-Tile DisplayPort SST Parallel Loopback Design Features 2.2. Agilex™ 7 F-Tile DisplayPort SST TX-only Design Features 2.3. Agilex™ 7 F-Tile DisplayPort SST RX-only Design Features 2.4. Design Components 2.5. Clocking Scheme 2.6. Interface Signals and Parameters
3. HDCP Over DisplayPort Design Example x
3.1. High-bandwidth Digital Content Protection (HDCP) 3.2. HDCP Over DisplayPort Design Example Architecture 3.3. Nios® V Processor Software Flow 3.4. Design Walkthrough 3.5. Protection of Encryption Key Embedded in FPGA Design 3.6. Debug Guidelines
3.4. Design Walkthrough x
3.4.1. Setting Up the Hardware 3.4.2. Generating the Design 3.4.3. Including HDCP Production Keys 3.4.4. Compiling the Design 3.4.5. Viewing the Results
3.4.3. Including HDCP Production Keys x
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) 3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1)
3.4.3.1. Storing Plain HDCP Production Keys in the FPGA (Support HDCP Key Management = 0) x
3.4.3.1.1. HDCP Key Mapping from DCP Key Files 3.4.3.1.2. hdcp1x_tx_kmem.v and hdcp1x_rx_kmem.v files 3.4.3.1.3. hdcp2x_rx_kmem.v file 3.4.3.1.4. hdcp2x_tx_kmem.v file
3.4.3.2. Storing Encrypted HDCP Production Keys in the External Flash Memory or EEPROM (Support HDCP Key Management = 1) x
3.4.3.2.1. Intel KEYENC 3.4.3.2.2. Key Programmer
3.5. Protection of Encryption Key Embedded in FPGA Design x
3.5.1. Security Considerations
3.6. Debug Guidelines x
3.6.1. HDCP Status Signals 3.6.2. Modifying HDCP Software Parameters 3.6.3. Frequently Asked Questions (FAQ)
1. DisplayPort Intel® FPGA IP Design Example Quick Start Guide
2. DisplayPort Intel® FPGA IP Design Examples
3. HDCP Over DisplayPort Design Example
4. Document Revision History for F-Tile DisplayPort Intel® FPGA IP Design Example User Guide

1.6. DisplayPort Intel® FPGA IP Design Example Parameters

Table 2.  DisplayPort Intel® FPGA IP Design Example QSF constraint for Agilex™ 7 F-Tile Devices
QSF Constraint Description
set_global_assignment -name VERILOG_MACRO "__DISPLAYPORT_support__=1" Enables DisplayPort custom SRC (Soft Reset Controller) flow.
Table 3.  DisplayPort Intel® FPGA IP Design Example Parameters for Agilex™ 7 F-Tile Devices
Parameter Value Description
Available Design Example
Select Design
  • None
  • DisplayPort SST Parallel Loopback without PCR
  • DisplayPort SST Parallel Loopback with AXIS Video Interface
  • DisplayPort RX-only
  • DisplayPort TX-only
 Select the design example to be generated.
  • None: No design example is available for the current parameter selection.
  • DisplayPort SST Parallel Loopback without PCR: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source without a Pixel Clock Recovery (PCR) module when you turn on the Enable Video Input Image Port parameter.
  • DisplayPort SST Parallel Loopback with AXIS Video Interface: This design example demonstrates parallel loopback from DisplayPort sink to DisplayPort source with AXIS Video interface when Enable Active Video Data Protocols is set to AXIS-VVP Full.
  • DisplayPort RX-only: This example design demonstrates an RX-only design. The Enable Video Input Image Port parameter must be disabled. The example design software will report the RX link status.
  • DisplayPort TX-only: This example design demonstrates a TX-only design. The Enable Video Input Image Port parameter must be disabled. The example design software will report the TX link status. The design will output color bars in 1080p format.
Design Example Files
Simulation On, Off Turn on this option to generate the necessary files for the simulation testbench.
Note: Simulation is not yet supported in this release.
Synthesis On, Off Turn on this option to generate the necessary files for Quartus® Prime compilation and hardware design.
Generated HDL Format
Generate File Format Verilog, VHDL Select your preferred HDL format for the generated design example fileset.
Note: This option only determines the format for the generated top level IP files. All other files (e.g. example testbenches and top level files for hardware demonstration) are in Verilog HDL format.
Target Development Kit
Select Board
  • No Development Kit
  • Agilex™ 7 I-Series SoC Development Kit FA
  • Agilex™ 7 I-Series SoC Development Kit FB
  • Custom Development Kit
 Select the board for the targeted design example.
  • No Development Kit: This option excludes all hardware aspects for the design example. The IP core sets all pin assignments to virtual pins.
  • Agilex™ 7 I-Series SoC FPGA Development Kit FA: This option automatically sets the project's target device to the AGIB027R31B1E1V. You may change the target device using the Change Target Device parameter, but Intel strongly recommends that you do not override the target device. If you require a different device, select the Custom Development Kit option. The IP core sets all pin assignments according to the development kit.
  • Agilex™ 7 I-Series SoC FPGA Development Kit FB: This option automatically sets the project's target device to the AGIB027R31B1E1VAA. You may change the target device using the Change Target Device parameter, but Intel strongly recommends that you do not override the target device. If you require a different device, select the Custom Development Kit option. The IP core sets all pin assignments according to the development kit.
  • Custom Development Kit: This option allows the design example to be tested on a third-party development kit with an Intel FPGA. The project's target device will be set using the target device of the current project. You are required to modify the pin assignments.
Target Device
Change Target Device On, Off Turn on this option and select the preferred device variant for the development kit.
Related Information
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