AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

Download PDF
ID 709310
Date 6/21/2022
Public
Document Table of Contents
Document Table of Contents x
1. Terms and Acronyms 2. Introduction 3. Prerequisites and Scope 4. System Design Guidelines Requirements 5. HDMI 2.1 Compliance Test Specification 6. Future System Level Optimization 7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines
4. System Design Guidelines Requirements x
4.1. Enabling PCB panel design 4.2. PCB Best Practices 4.3. System Link Budgeting Recommendations
4.3. System Link Budgeting Recommendations x
4.3.1. FPGA TX Settings 4.3.2. FPGA RX Settings
4.3.2. FPGA RX Settings x
4.3.2.1. Intel® Stratix® 10-specific RX Feature
5. HDMI 2.1 Compliance Test Specification x
5.1. Protocol IP Compliance Test Specification 5.2. Electrical Compliance Test Specification 5.3. Performance and Cost Considerations
6. Future System Level Optimization x
6.1. Availability of Redrivers or Retimers 6.2. The Intel Agilex® Platform
1. Terms and Acronyms
2. Introduction
3. Prerequisites and Scope
4. System Design Guidelines Requirements
5. HDMI 2.1 Compliance Test Specification
6. Future System Level Optimization
7. Document Revision History for AN 952: Intel® Arria® 10 and Intel® Stratix® 10 HDMI 2.1 System Design Guidelines

4.3. System Link Budgeting Recommendations

Platform link budgeting helps improve your experience by allocating sufficient loss on main board (with Intel® Arria® 10 or Intel® Stratix® 10 FPGA), PCB panel or daughtercard, and HDMI connectors (including cables).

Apply a generic redriver primarily to meet Insertion Loss at 12 Gbps. In a typical use case scenario, there is an estimated cable loss of 19 dB with two connectors.

Table 5.  Link Budgeting Distribution
Item Link Component Insertion Loss @12 Gbps Comment
1 FPGA → FMC → TX Redriver 5 dB TX FFE recommended
2 Redriver → HDMI connector 10 dB (+18 dB)

Minimize lowest loss

Budgets for cable loss
3 HDMI cable → Connector → RX Redriver → FPGA RX 19 dB+10 dB

Better Redriver/retimer
Note: Refer to Table 7 for jitter tolerance data.

Section Content
FPGA TX Settings
FPGA RX Settings

Level Two Title