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1. About the F-Tile 25G Ethernet Intel FPGA IP User Guide
2. About this IP
3. Getting Started
4. F-Tile 25G Ethernet Intel FPGA IP Parameters
5. Functional Description
6. Reset
7. Interfaces and Signal Descriptions
8. Control, Status, and Statistics Register Descriptions
9. F-Tile 25G Ethernet Intel FPGA IP User Guide Archive
10. Document Revision History for the F-Tile 25G Ethernet Intel FPGA IP User Guide
7.1. TX MAC Interface to User Logic
7.2. RX MAC Interface to User Logic
7.3. Transceivers
7.4. Transceiver Reconfiguration Signals
7.5. Avalon® Memory-Mapped Management Interface
7.6. Dynamic Reconfiguration Interface Signals
7.7. Miscellaneous Status and Debug Signals
7.8. Clock Signals
7.9. Reset Signals
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5.1.3.3. Length/Type Field Processing
This two-byte header represents either the length of the payload or the type of MAC frame.
- Length/type < 0x600—The field represents the payload length of a basic Ethernet frame. The MAC RX continues to check the frame and payload lengths.
- Length/type >= 0x600—The field represents the frame type. The following frame types are possible:
- Length/type = 0x8100—VLAN or stacked VLAN tagged frames (up to a total of two tags with value 0x8100). The MAC RX continues to check the frame and payload lengths.
- Length/type = 0x8808—Control frames. The next two bytes are the Opcode field that indicates the type of control frame. For pause frames (Opcode = 0x0001) and PFC frames (Opcode = 0x0101), the MAC RX proceeds with pause frame processing. In addition to processing any pause request, the IP core passes these frames to the RX client interface and updates the appropriate l1_rxstatus_data bits.
- For other field values, the MAC RX forwards the receive frame to the client.
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